Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer

Zheng, Li; Bakir, Muhannad S.

doi:10.1109/socc.2012.6398388

Cited by 3 publications

(1 citation statement)

References 10 publications

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“…To address this need, wafer-level batch fabricated solder microfluidic chip I/Os and fine-pitch electrical microbump I/Os have been recently demonstrated, as shown in Fig. 3 [17]. With this innovative chip I/O technology, this paper proposes and experimentally demonstrates a tierspecific MFHS in a two-tier stack.…”

Section: B Embedded Microfluidic Heat Sink In the Literaturementioning

confidence: 99%

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Zhang

Zheng

Bakir

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Cooling is a significant challenge for highperformance and high-power 3-D ICs. In this paper, tier-specific microfluidic cooling technology is proposed and experimentally evaluated in a 3-D stack. Different stacking scenarios are experimentally evaluated including: 1) a memory-on-processor stack; 2) a processor-on-processor stack with equal power dissipation; 3) a processor-on-processor stack with different power dissipations; and 4) a two-tier 3-D stack with each tier containing four cores along the flow direction. Compared with conventional microfluidic cooling, the tier-specific cooling is shown to reduce the pumping power by 37.5% by preventing overcooling when an operating temperature is specified. The results are benchmarked with an air-cooled heat sink. The impact of the lateral thermal gradient along the flow direction on the electrical performances, including leakage power and clock frequency, is analyzed.Index Terms-3-D IC, leakage power, microchannel heat sink, micropin-fin (MPF) heat sink, multicore processors.

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Section: B Embedded Microfluidic Heat Sink In the Literaturementioning

confidence: 99%

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Zhang

Zheng

Bakir

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Vertically integrated processor and memory module design for vector supercomputers

Egawa

Sato

Tada

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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3-D floorplanning algorithm to minimize thermal interactions

Vaisband

Friedman

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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An algorithm for including relative thermal interactions among different circuit modules within a 3-D system is introduced in this paper. Application of the proposed algorithm on MCNC and GSRC benchmark circuits is presented. The thermal behavior of a heterogeneous 3-D structure, consisting of a different number of modules and substrate materials, is evaluated to emulate the heat transfer characteristics of practical heterogeneous 3-D systems. The algorithm lowers thermal interactions between different modules while maintaining the peak temperature within a practical range. The thermal characteristics of the floorplan are evaluated using HotSpot and HotSpot Detailed 3-D and compared to a random floorplan. The recorded peak temperatures are within the practical range of on-chip temperatures.

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Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer

Cited by 3 publications

References 10 publications

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Vertically integrated processor and memory module design for vector supercomputers

3-D floorplanning algorithm to minimize thermal interactions

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