Electrical Backplane Equalization Using Programmable Analog Zeros and Folded Active Inductors

Chen, Jinghong; Saibi, Fadi; Lin, Jenshan; Azadet, K.

doi:10.1109/tmtt.2007.900342

Cited by 8 publications

(2 citation statements)

References 15 publications

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“…Using an equalizer is another popular way to solve the ISI problem. The circuits of an equalizer can be analog [14,15] or digital [10,16]. The equalizer based on the digital circuit is discussed in this thesis.…”

Section: Figure 24: Group Delay Of Channel B20mentioning

confidence: 99%

“…As pointed out in Chapter 2, the FFE can be implemented in the transmitter side or the receiver side. As at the receiver side, we do not have the clock information, most FFEs implemented at the receiver side are either an analog FFE [14,17] or a digital FFE using delay line variation between the taps [21]. The difference of the delay values increases jitter.…”

Section: Theory Of Ffe In the Digital Circuitmentioning

confidence: 99%

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A reduced power, 6-tap programmable pre-emphasis circuit

Cheng¹

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Section: Figure 24: Group Delay Of Channel B20mentioning

confidence: 99%

Section: Theory Of Ffe In the Digital Circuitmentioning

confidence: 99%

A reduced power, 6-tap programmable pre-emphasis circuit

Cheng¹

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A 5‐Gbps USB3.0 transmitter and receiver linear equalizer

Terzopoulos¹,

Laoudias²,

Plessas³

et al. 2014

Circuit Theory & Apps

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SummaryA USB3.0 compatible transmitter and the linear equalizer of the corresponding receiver are presented in this paper. The architecture and circuit design techniques used to meet the strict requirements of the overall link design are explored. Output voltage amplitude and de‐emphasis levels are programmable, whereas the output impedance is calibrated to 50Ω. A programmable receiver equalizer is also presented with its main purpose being to compensate for the channel losses; this is employed together with a DC offset compensation scheme. The 6.25‐GHz equalizer provides a 10 dB overall gain equalization and 5.5‐dB peaking at the maximum gain setting. Designed using a mature and well established 65 nm complementary metal oxide semiconductor process, the layout area is 400 µm × 210 µm for the transmitter core, and 140 µm × 70 µm for the equalizer core. The power consumption is 55 and 4 mW, respectively, from a 1.2 V supply at a data rate of 5 Gbps. The target application for such high‐speed blocks is to implement the critical part of the physical layer that defines the signaling technology of SuperSpeed USB3 PHY. However, identical iterations of the circuitry discussed can be used for similar high‐speed applications like the PCI express (PCIe). Copyright © 2014 John Wiley & Sons, Ltd.

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Equalization and pre-emphasis based LVDS transceiver

Matig-a¹,

Huang²

2013

Analog Integr Circ Sig Process

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Electrical Backplane Equalization Using Programmable Analog Zeros and Folded Active Inductors

Cited by 8 publications

References 15 publications

A reduced power, 6-tap programmable pre-emphasis circuit

A reduced power, 6-tap programmable pre-emphasis circuit

A 5‐Gbps USB3.0 transmitter and receiver linear equalizer

Equalization and pre-emphasis based LVDS transceiver

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