Electrical characteristics of 20-nm junctionless Si nanowire transistors

Park, Chan-Hoon; Ko, Myung-Dong; Kim, Ki‐Hyun; Baek, Rock‐Hyun; Sohn, Chang-Woo; Baek, Chang Ki; Park, Soo‐Young; Deen, M. Jamal; Jeong, Yoon‐Ha; Lee, Jeong-Soo

doi:10.1016/j.sse.2011.11.032

Cited by 143 publications

(45 citation statements)

References 8 publications

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“…Although the concentration of the devices has been varied along the entire active region, the devices could be produced with channel doping concentration in the order of 10 19 cm -3 and source/drain regions more strongly doped aiming at a decrement of the overall series resistance with the reduction of the incomplete ionization [4,26]. Figure 11 shows the series resistance of Junctionless nanowire devices as a function of the source/drain doping concentration (N sd ) with the channel doping concentration kept at N D =1X10 19 cm -3 .…”

Section: Source/drain Doping Concentrationsmentioning

confidence: 99%

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature

Doria¹,

Trevisoli²,

Souza³

et al. 2020

JICS

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The effect of the source/drain parasitic resistance (RS) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on RS has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on RS is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.

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Section: Source/drain Doping Concentrationsmentioning

confidence: 99%

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature

Doria¹,

Trevisoli²,

Souza³

et al. 2020

JICS

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“…The advantages of the JLT over the planar bulk MOSFET are (i) improved short-channel effect [37] and (ii) simplicity of fabrication. However, the JLT requires a higher gate work-function value to achieve desirable threshold voltage values (i.e., p + polycrystalline silicon is used for n-type tri-gate JLT instead of n + poly silicon and vice versa [35]).…”

Section: Junctionless Transistor (Jlt) [35 36]mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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“…Field effect Transistor (absence of physical p-n junction in the source or drain side) where only a uniformly doped channel has been present [6][7][8][9][10][11].This structure produces excellent immunity to SCEs (Short Channel Effects) and double-gate or multi-gate devices offer better scalability options. Besides, this device is simpler to fabricate and has less variability and better electrical properties than MOSFET.…”

Section: Introductionmentioning

confidence: 99%