Electrical characterization by sub-micron probing technique on 90 nm CMOS technology for failure analysis

Giret, C.; Faure, D.

doi:10.1109/ipfa.2004.1345621

Cited by 4 publications

(1 citation statement)

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“…Nano probing [30] was then performed on each suspected transistor in the NAND4 cell which identified the pMOS transistor receiving the C input signal as being non-responsive to the gate voltage.…”

Section: F Physical Failure Analysismentioning

confidence: 99%

Cell-Aware Test

Hapke¹,

Redemund²,

Glowatz³

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

159

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This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.Index Terms-Automatic test pattern generation, cell-aware test, defect-based test, defective parts, design for testability, failure analysis, FinFET test, logic testing, test data compression, transistor-level test.

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Section: F Physical Failure Analysismentioning

confidence: 99%