2003
DOI: 10.1109/led.2003.810879
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Electrical characterization of germanium p-channel MOSFETs

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Cited by 181 publications
(89 citation statements)
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“…Significant research on the high-j gate dielectrics HfO 2 , 17 23 and germanium-oxynitride 24 has been studied on the (100)Ge metal-oxide semiconductor (MOS) devices. Although excellent device performances were achieved using high-j gate dielectrics on bulk (100)Ge and oxide/(100)Ge band alignment properties, little attention has been devoted on the integration of high-j gate dielectrics on the epitaxial (110)Ge, (111)Ge, and the associated energy band alignment at each interface.…”
Section: Introductionmentioning
confidence: 99%
“…Significant research on the high-j gate dielectrics HfO 2 , 17 23 and germanium-oxynitride 24 has been studied on the (100)Ge metal-oxide semiconductor (MOS) devices. Although excellent device performances were achieved using high-j gate dielectrics on bulk (100)Ge and oxide/(100)Ge band alignment properties, little attention has been devoted on the integration of high-j gate dielectrics on the epitaxial (110)Ge, (111)Ge, and the associated energy band alignment at each interface.…”
Section: Introductionmentioning
confidence: 99%
“…Recently, high electron mobility in Ge n-channel metal-insulation-semiconductor field-effect transistors (n-MISFETs) with a sub-nm equivalent oxide thickness gate stack has been demonstrated, owing to appropriate gate stack designing, [1][2][3][4] in addition to the high hole mobility in Ge p-MISFET, which has already been reported. 5,6) Therefore, the most serious challenges for realizing practical scaled Ge CMOS are currently the reduction in parasitic resistance and the suppression of off-state leakage at the source=drain of MISFETs. In particular, to reduce the contact resistance at the metal=Ge interface, a reduction in Schottky barrier height (SBH) at the interface is definitely required.…”
mentioning
confidence: 99%
“…22 The calculated mobility of the planar FET, 313 cm 2 /V s, was larger than we found for our system, although this is not surprising given that the surfaces of the Ge nanowire FETs were unpassivated. Higher mobilities and smaller subthreshold slopes should be obtainable for future Ge nanowire FETs by deposition of a Ge oxynitride 23 or SiGe capping layer that could limit charge traps at the nanowire surface. Our bottom-up approach to device fabrication will allow such passivation to be carried out in situ following Ge nanowire synthesis, and this should lead to improved characteristics for both n-and p-type Ge nanowire FETs.…”
mentioning
confidence: 99%