Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

Ahn, Tae Jun; Choi, Byoung Geol; Lim, Sung Kyu; Yu, Yun Seop

doi:10.3390/mi10100637

Cited by 7 publications

(5 citation statements)

References 18 publications

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“…Therefore, it is necessary to fully analyze the electrical performance (such as the delay, power, the integration of logic circuits, and the stability of the SRAM considering electrical coupling [11,12] and interface trap charges) when designing M3DIC and M3D memories.…”

Section: Discussionmentioning

confidence: 99%

“…When fabricating a circuit with M3DI, the effects of interface trap charges and electrical coupling due to inter-layer dielectric (ILD) distances should be considered. Previous studies investigated electrical coupling with the distance of the ILD when the interface trap charge was ignored [7][8][9][10][11] and extracted SPICE parameters of the monolithic 3D inverter (M3DINV) for the circuit design simulation [12]. However, for a realistic circuit design simulation, it is necessary to extract the SPICE model parameters considering the interface trap charge.…”

Section: Introductionmentioning

confidence: 99%

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Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

Ahn

Lim

2021

Applied Sciences

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We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

Ahn

Lim

2021

Applied Sciences

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“…Conventional 3D-IC design approach stacks multiple substrates together with through-silicon-via (TSV) interconnects between substrates. But TSVs occupy significant substrate footprint since their diameter is in the range of 3-20µm, and in addition dummy TSV insertion overhead and keep-out-zone (KOZ) compromise the benefit brought by the vertical integration [1][2][3][4][5][6][7]. On the contrary, the vertical vias in M3D-IC technology are realized by small vias that are in the range of 20nm -100nm known as metal inter-layer via (MIV), thus reducing the silicon footprint consumption significantly compared to conventional 3D-IC approach.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

Vemuri,

Tida

2024

IEEE Access

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Transistor-level monolithic three-dimensional integrated circuit (M3D-IC) technology potential is compromised with the silicon footprint overhead caused by metal inter-layer via (MIV). To address this issue, we present a dual-purpose MIV-device utilization where MIV serves two purposes: 1. interconnect and 2. device terminal. A detailed study of the proposed MIV-devices specifically MIV-capacitor and MIVtransistor is performed and a strategy to extract level-3 Spice models is presented in this paper. Simulation results suggest that the basic logic gates designed with the opportunistic utilization of MIV-devices reduce the substrate utilization by up to 22% compared with the conventional transistor-level implementation in M3D-IC technology.

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“…In order to utilize these characteristics, various circuits with the M3D structure were studied [ 10 , 11 , 12 , 13 , 14 , 15 , 16 ]. Particularly, the 6T (or more than six transistors) SRAMs with M3D structure have been proposed and studied to increase density, which can achieve up to a 45% density increase [ 17 , 18 , 19 , 20 , 21 , 22 ].…”

Section: Introductionmentioning

confidence: 99%

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor

2022

Micromachines

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A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and one on the bottom tier in a monolithic 3D integration, respectively. The electrical characteristics and operation of the NFBFET in the M3D-FBFET-SRAM cell were investigated using a TCAD simulator. For SRAM operation, the optimum doping profile of the NFBFET was used for non-turn-off characteristics. For the M3D-FBFET-SRAM cell, the operation of the SRAM and electrical coupling occurring between the top and bottom tier transistor were investigated. As the thickness of interlayer dielectric decreases, the reading ‘ON’ current decreases. To prevent performance degradation, two ways to compensate for current level were suggested.

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Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

Cited by 7 publications

References 18 publications

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor

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