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We have suggested and developed a novel 6 photo‐mask process for the p‐channel poly‐Si thin film transistor TFT panel fabrication of active matrix organic light‐emitting diode AMOLED. By removing power line Vdd and bank photo process, we simplified the fabrication process from 8 to 6 mask steps. The p‐channel TFT fabricated by the 6 photo‐mask process had a field effect mobility of ∼80 cm2/Vsec, a sub‐threshold voltage swing of ∼0.3 V/dec., and a threshold voltage of ∼−2 V. Using the 6 photo‐mask process, we have successfully realized a 7‐inch WVGA 720×480 AMOLED panel, which is controlled by the voltage driving method.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

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