Parameter Extraction and Power/Performance Analysis of Monolithic 3-D Inverter (M3INV)

Ahn, Tae Jun; Perumal, Rakesh; Lim, Sung Kyu; Yu, Yun Seop

doi:10.1109/ted.2018.2885817

Cited by 7 publications

(9 citation statements)

References 10 publications

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“…This shows the validity of the HSPICE model. DC/AC and transient results were also verified [14] and used in the circuit simulation of various logic circuits in this study. Table 2 shows a summary of internal and external capacitances by metal lines (MLs) and monolithic inter-tier vias (MIVs) of M3DINV.…”

Section: Simulation and Discussionmentioning

confidence: 99%

“…( a ) Equivalent circuit of M3DINV [14] consisting of internal and external capacitances, where the capacitance caused by monolithic inter-tier vias (MIVs) and metal lines (MLs) are added. ( b ) Voltage transfer characteristics (VTC) of M3DINV [14]. V SS = 0 V and V DD = 1 V.…”

Section: Figurementioning

confidence: 99%

“…In previous studies, we investigated the electrical coupling of direct current (DC)/alterating current (AC) and transient device parameters in the monolithic 3D inverter (M3DINV) [13]. We proposed a new SPICE model to fully consider the investigated electrical coupling and extracted model parameters to create an M3DINV unit cell model for circuit simulation [14].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

et al. 2019

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In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

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Section: Simulation and Discussionmentioning

confidence: 99%

Section: Figurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

et al. 2019

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“…Recently, many problems occurring in designing next-generation integrated circuits (ICs) have been emerging, owing to continuous scaling for a metal-oxide-semiconductor field-effect transistor (MOSFET). The nanoscale MOSFET has a short channel effect, which increases the standby power by increasing leakage current, and has difficulty in controlling threshold voltage owing to the gate field influence becoming weak in a nanoscale channel [1,2]. Moreover, using MOSFETs to design high-performance ICs is difficult due to the physical limitations of MOSFETs being unable to have a subthreshold swing (SS) of less than 60 mV/dec at room temperature.…”

Section: Introductionmentioning

confidence: 99%

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

2021

Micromachines

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In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement IDS-VGS characteristics but could not accurately implement IDS-VDS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the IDS-VGS characteristics but also the IDS-VDS characteristics. A hybrid inverter and an integrate and fire (I&F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.

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“…JLFETs are advantageous for scale-down, surface mobility degradation, and short-channel effects [ 18 ]. A new circuit simulation model has been proposed in which the M3DIC composed of MOSFETs (M3DIC-MOSFETs) reflect direct current (DC)/alternating current (AC) and transient inter-layer electrical coupling [ 19 ]. However, owing to the absence of a JLFET compact model that considers electrical coupling between the tiers for the circuit simulation of M3DI structures, an accurate circuit simulation for M3DICs is not possible [ 20 , 21 , 22 , 23 ].…”

Section: Introductionmentioning

confidence: 99%

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Ahn

2020

Micromachines

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The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

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Parameter Extraction and Power/Performance Analysis of Monolithic 3-D Inverter (M3INV)

Cited by 7 publications

References 10 publications

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

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