Electrical Degradation of N-Channel Poly-Si TFT under AC Stress

Abstract

The degradation of n-channel poly-silicon thin film transistor ͑poly-Si TFT͒ has been investigated under dynamic voltage stress. The ON-current of TFT is 0.03 times the initial value after 1000 s stress. However, both the sub-threshold swing and threshold voltage almost kept well during the ac stress. The current crowding effect was rapidly increased with the increasing of stress duration. The creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. Moreover, the damaged regions were evidenced to be mainly near the source/drain regions according to the electrical analyses.Low-temperature polycrystalline-silicon thin film transistors ͑poly-Si TFTs͒ have been widely investigated for flat-panel applications such as active matrix liquid crystal display and active matrix organic light-emitting diode display. 1-4 Poly-Si TFTs can be fabricated on low-cost glasses because the maximum process temperature is lower than 600°C. The major advantage of the poly-Si TFT is a higher field effective mobility than that of the a-Si-based TFT. Moreover, the poly-Si TFT can be produced as complementary N-channel and P-channel transistors. Taking advantage of these features, poly-Si TFTs are applied for pixel TFTs and the driver circuits ͑e.g., scan driver͒. If the mobility of poly-Si TFTs is further increased, this poly-Si technology will realize the system on panel ͑SOP͒ which will integrate memory, CPU, and display. 5 However, the traps of grain structures play an important role for the electrical properties and stabilities of poly-Si TFTs. TFT devices in functional circuits serve as the switches and suffer the high-frequency voltage pulses. Previous research reports have shown a relationship between the creation of states and hot-carriers effect by performing dc stress. 6,7 The degradation mechanism of n-channel TFT under dynamic voltage stress, however, has not yet been clarified. 8,9 The degraded TFT will seriously influence the operation of the circuits. In this study, the degradation under dynamic operation for poly-Si n-channel TFT will be investigated by electrical analysis in detail. ExperimentalN-channel poly-Si TFTs with top-gate structure were fabricated on a glass substrate without lightly doped drain ͑LDD͒. First, a 50 nm thick amorphous silicon ͑a-Si͒ film was deposited by plasmaenhanced chemical vapor deposition ͑PECVD͒, and, subsequently, the films were dehydrogenated by furnace annealing. After dehydrogenation, the a-Si films were crystallized by XeCl excimer-laser. The power of the line-shaped beam was 350 mJ/cm 2 . Following the laser process, 100 nm thick gate oxide was deposited by PECVD. Then, the implantation was adopted to define the source/drain ͑S/D͒ region. Then an annealing process was performed to activate the dopant impurities. MoW was sputtered as a gate metal. The dimensions of TFTs in this work were L = 9 m, W = 6 m and the overlap of gate metal and S/D junction is 1 m. The cross-sectional views of TFTs were illustrated in Fig. 1...

Dynamic degradation mechanisms of low temperature polycrystalline silicon thin-film transistors

“…Similarly, the device degradation solely depends on the pulse transition of V g , rather than high or low V g biases. It was observed that shortening t f enhances the degradation while t r has little impact on the degradation [5][6][7][8][9]. A dynamic HC mechanism associated with V g switching controls the degradation [5][6][7][8][9]].…”

“…It was observed that shortening t f enhances the degradation while t r has little impact on the degradation [5][6][7][8][9]. A dynamic HC mechanism associated with V g switching controls the degradation [5][6][7][8][9]]. An earlier model proposes that as V g pulse swings from ON state to OFF state (determined by device V th ), some remaining channel electrons that have no enough time to return S/D will be exposed to a high coupling electric field and to be accelerated to HCs [7][8].…”

“…INTRODUCTION Low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) are promising candidates for realizing active-matrix display system on a panel for either LCD or OLED [1]. TFTs' device reliability is always a concern for such applications, on which previous investigations covered both direct current (dc) and alternative current (ac) stress conditions [2][3][4][5][6][7][8][9]. With no doubt, ac stress conditions are more realistic considering the actual operation conditions of TFT circuits.…”

“…It means that DC mechanism dominates the degradation of MOSFETs. For LTPS TFTs, although they are also field effect devices similar to MOSFETs, it will be shown that various dynamic degradation mechanisms are involved and dominate the degradation under ac stress conditions [4][5][6][7][8][9].In this paper, device degradation of LTPS TFTs under dynamic drain pluses (V d ), gate pluses (V g ), and synchronized V g /V d pulses are reviewed. The stress pulses could be positive, negative and bipolar according to the pulse base voltage (V g_b ) and its amplitude (V g_a ), as shown in Fig.…”

“…It means that DC mechanism dominates the degradation of MOSFETs. For LTPS TFTs, although they are also field effect devices similar to MOSFETs, it will be shown that various dynamic degradation mechanisms are involved and dominate the degradation under ac stress conditions [4][5][6][7][8][9].…”