Adipose-derived stem cells (ADSCs) have shown great promise for the treatment of myocardial infarction (MI), although their potential therapeutic mechanism remains poorly understood. Growing evidence has implicated microRNAs (miRNAs or miRs) in the biological processes whereby ADSCs could ameliorate cardiovascular disease. In this study, we explored the contribution of miR-34a-5p down-regulation to the protective actions of ADSCs against MI. We initially identified the interaction between miR-34a-5p and C1q/tumor necrosis factor-related protein-9 (CTRP9) through in silico analysis. We next tested the effects of miR-34a-5p and CTRP9 on the expression of extracellular signal-regulated kinase 1 (ERK1), matrix metalloproteinase-9 (MMP-9), nuclear factor (erythroid-derived 2)-like 2 (NRF2), and antioxidant proteins [manganese superoxide dismutase (MnSOD), and heme oxygenase-1 (HO-1)] through gain-and loss-of-function tests. In other experiments, we assessed the proliferation, migration, and apoptosis of ADSCs using the EdU assay, scratch test, Transwell assay, and flow cytometry. Finally, we studied whether miR-34a-5p/CTRP9 axis could modulate the protective effect of ADSCs against MI during stem cell transplantation in MI mouse models. miR-34a-5p could target and down-regulate CTRP9 in cardiomyocytes. Down-regulated miR-34a-5p increased the expression of ERK1, MMP-9, NRF2, MnSOD, and HO-1, whereas downregulation of miR-34a-5p or up-regulation of CTRP9 in vitro promoted ADSC proliferation and migration and inhibited ADSC apoptosis. Moreover, miR-34a-5p down-regulation or CTRP9 up-regulation promoted the protective role of ADSCs against MI damage in vivo. Thus, inhibition of miR-34a-5p may facilitate ADSC's protective function against MI damage by stimulating the expression of CTRP9.

The degradation of n-channel poly-silicon thin film transistor ͑poly-Si TFT͒ has been investigated under dynamic voltage stress. The ON-current of TFT is 0.03 times the initial value after 1000 s stress. However, both the sub-threshold swing and threshold voltage almost kept well during the ac stress. The current crowding effect was rapidly increased with the increasing of stress duration. The creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. Moreover, the damaged regions were evidenced to be mainly near the source/drain regions according to the electrical analyses.Low-temperature polycrystalline-silicon thin film transistors ͑poly-Si TFTs͒ have been widely investigated for flat-panel applications such as active matrix liquid crystal display and active matrix organic light-emitting diode display. 1-4 Poly-Si TFTs can be fabricated on low-cost glasses because the maximum process temperature is lower than 600°C. The major advantage of the poly-Si TFT is a higher field effective mobility than that of the a-Si-based TFT. Moreover, the poly-Si TFT can be produced as complementary N-channel and P-channel transistors. Taking advantage of these features, poly-Si TFTs are applied for pixel TFTs and the driver circuits ͑e.g., scan driver͒. If the mobility of poly-Si TFTs is further increased, this poly-Si technology will realize the system on panel ͑SOP͒ which will integrate memory, CPU, and display. 5 However, the traps of grain structures play an important role for the electrical properties and stabilities of poly-Si TFTs. TFT devices in functional circuits serve as the switches and suffer the high-frequency voltage pulses. Previous research reports have shown a relationship between the creation of states and hot-carriers effect by performing dc stress. 6,7 The degradation mechanism of n-channel TFT under dynamic voltage stress, however, has not yet been clarified. 8,9 The degraded TFT will seriously influence the operation of the circuits. In this study, the degradation under dynamic operation for poly-Si n-channel TFT will be investigated by electrical analysis in detail. ExperimentalN-channel poly-Si TFTs with top-gate structure were fabricated on a glass substrate without lightly doped drain ͑LDD͒. First, a 50 nm thick amorphous silicon ͑a-Si͒ film was deposited by plasmaenhanced chemical vapor deposition ͑PECVD͒, and, subsequently, the films were dehydrogenated by furnace annealing. After dehydrogenation, the a-Si films were crystallized by XeCl excimer-laser. The power of the line-shaped beam was 350 mJ/cm 2 . Following the laser process, 100 nm thick gate oxide was deposited by PECVD. Then, the implantation was adopted to define the source/drain ͑S/D͒ region. Then an annealing process was performed to activate the dopant impurities. MoW was sputtered as a gate metal. The dimensions of TFTs in this work were L = 9 m, W = 6 m and the overlap of gate metal and S/D junction is 1 m. The cross-sectional views of TFTs were illustrated in Fig. 1...

In this work, the characteristics of a p-type polysilicon thin-film transistor ͑poly-Si TFT͒ with dynamic bias stress were investigated. The ac stress is operated with the constant drain voltage ͑15 V͒ and the varying gate voltage ͑0 to 15 V͒ to degrade the devices. There are some phenomena which cannot be completely explained by the typical negative bias temperature instability ͑NBTI͒ mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could raise the channel temperature and cause the dissociation of the Si-H bonds at the poly-Si/SiO 2 interface due to Joule heating. The released hydrogen reacts with SiO 2 and causes the fixed charge in the gate oxide. Thus, the degradation of the electrical characteristics of device is mainly dominated by the self-heating-induced NBTI effect.Low-temperature polycrystalline silicon thin-film transistors ͑LTPS TFTs͒ have been widely investigated for flat-panel applications. Given its high field-effect mobility and driving current, poly-Si TFTs can integrate both a pixel array and peripheral circuits on a single glass substrate to realize system-on-panel displays. [1][2][3][4] Recently, in p-channel poly-Si TFTs, a negative bias temperature instability ͑NBTI͒ has been found to cause an important reliability problem for the device degradation. 5 The degradation is caused mainly by the dissociation of the Si-H bonds, and can be thermally and electrically activated. 6 As well as NBTI, self-heating should be considered. Because poly-Si TFTs are fabricated on glass substrates which have poor thermal conductivity, heat generated by Joule heating cannot be efficiently dissipated during the operation of devices and thus cause NBTI degradation. Hence, the self-heating effect is a very important issue in poly-Si TFTs degradation and may severely affect circuit performance. 7 Self-heating under dc stress in a p-channel poly-Si TFT has been measured using an infrared thermal detector. 8 However, the relationship between self-heating and NBTI under ac stress has not been clearly elucidated. Additionally, when poly-Si TFTs function as driver circuits, the device characteristics are affected by high-frequency voltage pulse operations. 9 Therefore, a detailed understanding of the degradation mechanism under dynamic operation is important.This work studies the instability and degradation mechanism of p-channel TFTs under dynamic stress by analyzing device characteristics, interface traps, and grain boundary trap densities before and after ac stress. ExperimentalThe p-channel poly-Si TFTs with a top-gate structure were fabricated on a glass substrate without a lightly doped drain. First, a thin layer of amorphous silicon ͑a-Si͒ ͑50 nm thickness͒ was deposited by plasma-enhanced chemical vapor deposition ͑PECVD͒ on glass substrates. The a-Si film was crystallized by a XeCl excimer laser. The power of the line-shaped beam was 350 mJ/cm 2 . After the laser process, 80 nm thick gate oxide was deposited by PECVD. Th...

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