Electrical hysteresis in p-GaN metal–oxide–semiconductor capacitor with atomic-layer-deposited Al₂O₃ as gate dielectric

Abstract

The electrical hysteresis in current–voltage (I–V) and capacitance–voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal–oxide–semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I–V scans occurred not at 0 V but at −4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg–Ga–Al–O oxidized layer with a trap density on the order of 1013 cm−2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg–Ga–Al–O layer via the Poole–Frenkel mechanism.

Dynamic Observation and Theoretical Analysis of Initial O2 Molecule Adsorption on Polar and m-Plane Surfaces of GaN

“…The metal–oxide–semiconductor (MOS) structure has been used for suppression of leak currents at the gate electrode, high speed on/off switching, and normally-off operation in power electronic devices . However, the density of defects at the interface between the GaN layer and the oxide layer must be reduced , to enhance the interface quality and improve the performance and reliability for the commercial application of vertical GaN power devices. Conventionally, an oxide layer of Al 2 O 3 or SiO 2 is deposited on the GaN layer.…”

A transient simulation approach to obtaining capacitance–voltage characteristics of GaN MOS capacitors with deep-level traps

“…[27][28][29][30][31][32] There are also many works concerning MOS capacitor modeling using materials other than GaN. [33][34][35][36][37] GaN MOS capacitors have also been thoroughly studied experimentally, focusing on their interface traps, [38][39][40][41][42][43][44] which have stronger effects than the bulk traps in general.…”

Passivation of hole traps in SiO2/GaN metal-oxide-semiconductor devices by high-density magnesium doping

“…17,18) In contrast, there are few reports on p-type GaN MOS capacitors that had well-behaved capacitance-voltage (C-V ) characteristics. [19][20][21][22][23][24] Because of the significant number of hole traps located near the oxide/GaN interfaces, a large C-V hysteresis is usually observed for p-type MOS capacitors. 25) Even worse, the surface potential of GaN is pinned and an ideal amount of hole accumulation at the MOS interface hardly occurs regardless of the gate dielectric materials used.…”

“…25) Even worse, the surface potential of GaN is pinned and an ideal amount of hole accumulation at the MOS interface hardly occurs regardless of the gate dielectric materials used. Although GaO x layers at the oxide/GaN interface and/or disordered Mg-segregation layers at the GaN surface might be the origins of the hole traps, 20,21,25,26) the details of the hole trapping mechanism remain unclear. Recently, we demonstrated good C-V characteristics for SiO 2 /p-GaN MOS capacitors fabricated by high-dose Mg-implantation and dopant activation by means of ultra-high-pressure annealing (UHPA) at 1400 °C.…”