Electrical performance of bumpless build-up layer packaging

Braunisch, Henning; Towle, Steven N.; Emery, R.D.; Hu, Chuan; Vandentop, Gilroy

doi:10.1109/ectc.2002.1008120

Cited by 43 publications

(6 citation statements)

References 13 publications

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“…A compilation of these techniques can be found in [19]. Even for high-performance microprocessors a concept for chip embedding has been presented recently [20]. The main advantages of integrating active chips into a substrate are the increased electrical performance by shorter interconnects and therefore lower inductances, increased reliability by lower stresses compared to flip chip assembly and a higher interconnect density.…”

Section: Embedded Componentsmentioning

confidence: 99%

Stackable system-on-packages with integrated components

Becker

Jung

Ostmann

et al. 2004

IEEE Trans. Adv. Packag.

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In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.Index Terms-Embedded passives, modular systems, molded interconnect device (MID), packaging, system-on-package (SOP).

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Section: Embedded Componentsmentioning

confidence: 99%

Stackable system-on-packages with integrated components

Becker

Jung

Ostmann

et al. 2004

IEEE Trans. Adv. Packag.

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“…In 2002, Intel proposed an experimental bumpless build-up layer (BBUL) technology that is characterized by the absence of a conventional core and a direct extension of the outermost metallization layers of the die into the overall thin substrate by eliminating bumps (C4s) on the die [15]. This technology provides the advantages of small electrical loop inductance for power delivery and minimizes discontinuities for high-speed signaling.…”

Section: Alternative Technologiesmentioning

confidence: 99%

The evolution of build-up package technology and its design challenges

Blackshear

Cases²,

Klink

et al. 2005

IBM J. Res. & Dev.

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This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

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“…The characteristics of organic substrate process make it possible for variable applications. By specially designed structure that embedding the chip into the substrate, it was indicated that the organic substrate process can achieve very high performance such as CiP (IZM) [7][8][9][10], BBUL (Intel) [11,12], or HDI (GE). …”

Section: Introductionmentioning

confidence: 99%

Wafer level chip stacked module by embedded IC packaging technology

Chien¹,

Shen²,

Chang³

et al. 2007

2007 International Microsystems, Packaging, Assembly and Circuits Technology

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Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50µm thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by dielectric layers (Ajinomoto build up film, ABF) lamination. Vias to both the pads on the analog chips and digital wafers were done by UV Laser drilling process. After surface treatment and seed layer deposition, Cu plating process was adapted for the the via filling and traces patterning to form the interconnection between the chips and the component IO pads. Results of this study showed the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. By the described process integration, vertical chip stacked and embedded module within 300µm thickness, excluding the solder ball, could be demonstrated. All the realization of this small size module will be revealed in detail. Severe reliabilty tests such as the 288 o C solder dipping and 260 o C level 3 pre-conditioning test were carried out to further clarify the component property. The corresponding failure analysis will be carried out to further clarify the key points of the whole demonstration.

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Electrical performance of bumpless build-up layer packaging

Cited by 43 publications

References 13 publications

Stackable system-on-packages with integrated components

Stackable system-on-packages with integrated components

The evolution of build-up package technology and its design challenges

Wafer level chip stacked module by embedded IC packaging technology

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