Electrical Properties of CeO2/La2O3Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Kouda, Miyuki; Suzuki, Takuya; Kakushima, Kuniyuki; Ahmet, Parhat; Yasuda, Tetsuji

doi:10.1143/jjap.51.121101

Cited by 11 publications

(3 citation statements)

References 29 publications

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“…Among these methods, ALD is considered an attractive technique for obtaining high-quality La 2 O 3 films due to its intrinsic self-limiting growth mode. ALD offers several advantages, including the ability to control film thickness by adjusting the number of deposition cycles, low pollution at low deposition temperatures for selflimiting surface reactions, and better film uniformity and conformity compared with other deposition techniques [14][15][16][17][18]. To utilize the benefits of ALD, it is crucial to explore and synthesize new precursors with high volatility and stability.…”

Section: Introductionmentioning

confidence: 99%

Atomic Layer Deposition of La2O3 Film with Precursor La(thd)3-DMEA

et al. 2023

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In this paper, a new precursor La(thd)3-DMEA (thd = 2,2,6,6-tetramethyl-3,5-heptanedione, DMEA = N,N′-dimethylethylenediamine) was synthesized and characterized with 1H-NMR and X-ray single crystal diffraction. The thermal properties of La(thd)3-DMEA were checked by thermogravimetric analysis (TGA), which confirmed that the volatility and suitability of La(thd)3-DMEA are suitable for atomic layer deposition (ALD). We studied the atomic layer deposition of La2O3 films on a SiO2 surface with La(thd)3-DMEA and O3 as precursors. Self-limiting deposition behaviors were found for the prepared films. The purity and surface morphology of the as-grown La2O3 films, which possessed a constant growth rate of ~0.4 Å/cycle at 250–280 °C, were confirmed by XPS, SEM, and AFM. The results show that La(thd)3-DMEA is a suitable precursor for the atomic layer deposition of La2O3 film.

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Section: Introductionmentioning

confidence: 99%

Atomic Layer Deposition of La2O3 Film with Precursor La(thd)3-DMEA

et al. 2023

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“…Whereas promising results have been shown for deposited oxides such as SrO and BeO (20,21), achieving controlled and reproducible thickness in the sub-nm regime (which is necessary given the relatively low dielectric constant of the dielectrics most suitable for integration as IL) is extremely challenging for any deposition method. The formation of a silicate IL by thermal reaction is especially interesting in this respect, since it can potentially provide excellent thickness control in the sub-nm regime and since many silicates (especially those formed from lanthanide oxides) have been reported to achieve excellent interface quality with Si (22)(23)(24)(25)(26).…”

Section: Introductionmentioning

confidence: 99%

(Invited) TmSiO as a CMOS-Compatible High-k Dielectric

2016

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Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

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“…During the past two decades, rare earth oxides (Y 2 O 3 , La 2 O 3 , Nd 2 O 3 , etc.) used as alternative gate dielectric materials have been extensively studied [4]. In particular, due to its high k value (approximately 27) and large band gap (approximately 5.3 eV), lanthanum oxide (La 2 O 3 ) is considered as one of the most promising alternative for HfO 2 to achieve a more aggressive downscaling of the EOT [5].…”

Section: Introductionmentioning

confidence: 99%

Silicon diffusion control in atomic-layer-deposited Al2O3/La2O3/Al2O3 gate stacks using an Al2O3 barrier layer

Wang¹,

Liu²,

Fei³

et al. 2016

Nano Online

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In this study, the physical and electrical characteristics of Al 2 O 3 /La 2 O 3 /Al 2 O 3 /Si stack structures affected by the thickness of an Al 2 O 3 barrier layer between Si substrate and La 2 O 3 layer are investigated after a rapid thermal annealing (RTA) treatment. Time of flight secondary ion mass spectrometry (TOF-SIMS) and X-ray photoelectron spectroscopy (XPS) tests indicate that an Al 2 O 3 barrier layer (15 atomic layer deposition (ALD) cycles, approximately 1.5 nm) plays an important role in suppressing the diffusion of silicon atoms from Si substrate into the La 2 O 3 layer during the annealing process. As a result, some properties of La 2 O 3 dielectric degenerated by the diffusion of Si atoms are improved. Electrical measurements (C-V, J-V) show that the thickness of Al 2 O 3 barrier layer can affect the shift of flat band voltage (V FB ) and the magnitude of gate leakage current density.

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Electrical Properties of CeO₂/La₂O₃Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and Atomic Layer Deposition

Cited by 11 publications

References 29 publications

Atomic Layer Deposition of La2O3 Film with Precursor La(thd)3-DMEA

Atomic Layer Deposition of La2O3 Film with Precursor La(thd)3-DMEA

(Invited) TmSiO as a CMOS-Compatible High-k Dielectric

Silicon diffusion control in atomic-layer-deposited Al2O3/La2O3/Al2O3 gate stacks using an Al2O3 barrier layer

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