The presence of grain boundaries (GBs) in polycrystalline high-κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2)-based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown.

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The authors investigated the optimal growth conditions for atomic layer deposition of La2O3 using tris(iso-propylcyclopentadienyl) lanthanum, La(iPrCp)3, and H2O, and identified two necessary conditions for achieving self-limiting growth: A low growth temperature (Ts) of 150 °C–175 °C and an extremely long purging after the H2O feed. Low Ts was also preferable for improving the electrical properties of the metal-oxide-semiconductor devices such as the dielectric constant (k), leakage current, and effective mobility. As for the H2O feed time, a long feed resulted in increased interface-trap density, while a short feed resulted in increased leakage. An H2-plasma treatment inserted after the thin-La2O3 (0.5 nm) film growth reduced the leakage current by 3 orders of magnitude compared to the control sample. An MgO capping on the La2O3 remarkably increased the effective k value; however, it degraded the effective mobility. Transmission electron microscopy indicated that the k-value improvement by the MgO capping is due to suppression of La-silicate formation.

A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (k av ) of 17.4 has been obtained and an extremely low gate leakage current (J g ) of 0.65 A/cm 2 . The flatband voltage (V fb ) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the V fb to positive direction. IntroductionThe scaling in gate dielectric below equivalent oxide thickness (EOT) of 0.7 nm essentially requires a technique to directly contact high-k dielectrics to Si substrate with good interfacial property [1]. Several techniques, including cycle deposition and annealing, or oxygen scavenging process, have been so far reported to achieve a direct contact of high-k/Si structure [2,3]. The high-k/Si interface with HfO 2 is sensitive to the oxygen partial pressure during the process, so that one must choose a process within a window to achieve a direct high-k/Si structure (Fig.1). On the other hand, La 2 O 3 can achieve a direct high-k/Si interface by forming a silicate layer with fairly nice interface properties [4]. However, the excess formation of silicate results in the increase in EOT. CeO 2 has an advantage in the wide process window to achieve a direct high-k/Si interface. In terms of gate leakage current (J g ), silicates have advantage in widening the band gap at the cost of EOT (Fig.2). Therefore, this work focuses on the combination of a Si-rich Ce-silicate with La 2 O 3 to achieve a direct high-k/Si interface with both reduction in J g and EOT.

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