Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS

Misra, Veena; Zhong, Huicai; Lazar, H.

doi:10.1109/led.2002.1004233

Cited by 75 publications

(36 citation statements)

References 9 publications

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“…Stacked metal layers used in the gate structure have been investigated. Misra et al [10] reported that a metal gate stack using Ru-Ta alloys could yield a work function compatible with nMOS. Lin et al [11] implanted N into a Mo gate that was suitable for nMOS.…”

Section: Interface Dipole Formation In Mos Stackmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond, there are still many challenges to be solved. Among the various technologies to tackle these problems, interface dipole engineering (IDE) is an effective method to improve the performance, particularly, modulating the effective work function (EWF) of metal gates. Because of the different electronegativity of the various atoms in the interfacial layer, a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack. This paper reviews the interface dipole formation induced by different elements, recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation, and mechanism of IDE. high-k dielectrics, metal gate, interface dipole, MOS stack, effective work function Citation:Huang A P, Zheng X H, Xiao Z S, et al. Interface dipole engineering in metal gate/high-k stacks. Chin Sci Bull, 2012, 57: 28722878, doi: 10.1007/s11434-012-5289-6As poly-Si/SiO 2 is replaced by metal gate/high-k stacks in the 45 nm MOS technological node and beyond, the interface becomes more complicated and there are still many challenges to be solved [1,2], such as the flatband voltage shift (V fb shift) [3]. Hence, the properties of the high-k layer must be reconsidered carefully. It has recently been reported that the interface dipole can induce potential difference across the interface and change the band alignment of the MOS stack, and this phenomenon can be exploited to modulate the V fb shift [4][5][6]. Elemental doping can also improve the performance of the high-k layer. Interface dipole engineering (IDE) by varying the dopants or inserting capping layers has attracted much attention in MOS technology. Not only can this technique control the V fb shift, but also the properties of the high-k dielectrics can be improved [7]. This paper reviews the formation of interface dipole, recent research progresses on IDE and effective work function (EWF) modulation, as well as mechanism of IDE in metal gate/high-k MOS stacks. Interface dipole formation in MOS stackTo control the threshold voltage (V th ), work function of a metal gate should be near the conduction band of Si (~4.3 eV) for nMOS and valence band (~5.2 eV) for pMOS. However, only very few metals can satisfy these requirements and furthermore, when a metal is in contact with the high-k layer, its Fermi-level will tend to be at the neutral level of the high-k layer. This phenomenon is called Fermi-level pinning (FLP) which causes EWF of the nMOS (pMOS) to be much greater (smaller) than the corresponding work function in vacuum [8]. The electron density in the metal gate can also influence the EWF [9]. Stacked metal layers used in the gate structure have been investigated. Misra et al. [10] reported that a metal gate stack using Ru-Ta alloys could yield a work function compatible with nMOS. Lin et al. [11] implanted N into a Mo gate that was

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Section: Interface Dipole Formation In Mos Stackmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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“…However, intrinsic channel DG MOSFETs need to rely solely on gate work function to achieve multiple threshold voltages on a chip due to the absence of body doping, which is an efficient tool to adjust the threshold voltage in DG MOSFETs with doped channels [11,12]. In the past few years, many efforts including implanted metals [13], fully silicided gates [14][15][16], alloy metals [17][18][19], novel high-κ dielectric materials [20] and metal bilayers [21] have been reported, but none has been completely successful in integrating metals with tunable work function in DG MOSFETs due to technological difficulties [22]. Therefore, DG MOSFETs with suitably doped channels seem to be the easiest option from a fabrication point of view, and are seriously being investigated to set appropriate threshold voltages [12,23,24].…”

Section: Introductionmentioning

confidence: 99%

Threshold Voltage Control through Layer Doping of Double Gate MOSFETs

Joseph¹,

George²,

Mathew³

2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures-one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre-are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

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“…The three key points for selection of gate electrode materials are work function, thermal stability, and lower resistivity. So far, many types of materials have been investigated to replace poly-silicon, such as pure metals [2][3][4][5][6], binary alloys [7][8][9][10], metal nitrides [11][12][13][14][15], metal carbides [16], and fully silicided Si (FUSI) [17][18][19][20]. Of these, the refractory transition metal nitrides are of interest owing to their good thermal stability, good oxygen diffusion barrier characteristics, and tunable work function.…”

Section: Introductionmentioning

confidence: 99%