Electro-Thermal Characteristics of Junctionless Nanowire Gate-All-Around Transistors Using Compact Thermal Conductivity Model

Kumar, Nitish; Kumar, Sushil; Kaushik, Pragyey Kumar; Gupta, Ankur; Singh, Pushpapraj

doi:10.1109/ted.2023.3268249

Cited by 16 publications

(3 citation statements)

References 41 publications

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“…where µ n0 is the without strain mobility, m nl and m nt are the electron longitudinal and transverse masses in the sub-valley, respectively, and F n is the quasi-Fermi level of electrons. Some additional models are also used in simulation, such as hydrodynamic, bandgap narrowing, density gradient, mobility degradation (scattering and high field effects), band-to-band tunneling, and SRH recombination, which are discussed in detail in [9,[23][24][25]. The model calibration results with experimental data of JL-NW GAA FET [12] are verified, as shown in figure 3, which shows well agreement between simulation and experimental data.…”

Section: Computational Physical Modelmentioning

confidence: 69%

“…However, the junctionless nanowire (JL-NW) GAA FETs were shown to have better performance * Author to whom any correspondence should be addressed. [8], less electronic noise compared to GAA FETs [4], and better electrothermal performance [9]. The piezoresistive coefficient and electron mobility are also enhanced by reducing the doping concentration with tensile strain [10].…”

Section: Introductionmentioning

confidence: 99%

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Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Kumar,

Joshi,

Gupta

et al. 2024

Nanotechnology

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In this paper, the piezoresistive sensitivity is enhanced by applying uniform mechanical stress (MS) on the multi-nanosheet (NS) channels of sub-5 nm junctionless field-effect transistors (FETs). The piezoresistivity of the sensing device is boosted by narrowing channel conductivity using low gate biasing and reducing physical channel width, resulting in the maximum (~6 times higher) sensitivity observed in the subthreshold regime compared to the ON-state condition. In addition, the sensitivity is extensively increased by ~30.3% near the threshold voltage (VTH) with horizontally multi-NS stacking due to the uniform MS distribution on the multi-NS channels, which can sense slight deflection of pressure on the circular diaphragm. These results show that the tunable sensitivity of junctionless multi-channel devices is superior to the inversion mode, a consequence of the less scattering effect, better thermal stability, and low electronic noise.

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Section: Computational Physical Modelmentioning

confidence: 69%

Section: Introductionmentioning

confidence: 99%

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Kumar,

Joshi,

Gupta

et al. 2024

Nanotechnology

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“…In addition, channel pinch-off causes the drain current to be saturated. To overcome these challenges, carbon nanotube field effect transistors (CNTFETs) [8][9][10][11], FETs based on nanowire structures (NW-FETs) [12][13][14][15], thin-film transistors (TFTs) [16,17], and field effect diodes (FEDs) [18][19][20][21][22] were proposed. CNTFETs are characterized as transistors with high mobility, low power consumption, and small size.…”

Section: Introductionmentioning

confidence: 99%

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

GolshanBafghi,

Rezaei,

Ghafouri

et al. 2023

JCHAR

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Nanostructured solid-state devices demonstrate prominent electronic transport properties and thus represent powerful building blocks for a wide range of analog and digital integrated circuits and systems. In this study, the integration of the side-contacted field effect diode (S-FED) with the silicon nanowire concept is pursued to create a device that maintains a substantial aspect ratio while delivering suitable execution. The nanowire side-contacted FED (NW-SFED), referred to as this apparatus, exhibits the capability to achieve an exceptionally high ON/OFF current ratio of 4×10 8 , allowing for efficient switching between ON and OFF states. While the downscaling of the planar CMOS technology has faced severe constraints, this characteristic is featured as a figure of merit for the NW-SFED device. Accordingly, the device can also be used in a coordinated device-circuit co-design framework as a promising candidate to mitigate noise, delay, and energy. Herein, a quantitative evaluation of NW-SFED's performance is conducted utilizing a semiconductor drift-diffusion solver to explore how variations in channel length, device width, as well as the dimensions of the n + and p + doped regions in the source and drain, respectively, influence its operational characteristics. The impact of the channel length, spacer length and device width on NW-SFED fabrication turned out to be negligible. In contrast, the thickness of doped regions emerged as the critical parameter in the fabrication process.

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Machine Learning‐Guided Design of 10 nm Junctionless Gate‐All‐Around Metal Oxide Semiconductor Field Effect Transistors for Nanoscaled Digital Circuits

Ouchen,

Berghout,

Djeffal

et al. 2024

Physica Status Solidi (a)

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In this paper, we introduce an innovative design approach based on combined numerical simulations and machine learning (ML) analysis to investigate the design key parameters of ultra‐low scale junctionless gate‐all‐around (JLGAA) field‐effect transistor (FET) devices. To this end, precise 3D numerical models that incorporate quantum effects and ballistic transport are employed to simulate the current–voltage (I–V) characteristics of 10 nm‐scale JLGAA FET devices. The influence of design parameter variations and high‐k dielectric material on the subthreshold characteristics is thoroughly examined. Various ML algorithms were employed to analyze and classify the key design parameters influencing the subthreshold figures‐of‐merit (FoMs), the subthreshold swing (SS) factor and ION/IOFF ratio. The obtained results highlight that channel radius and channel doping design parameters are particularly important for affecting swing factor behavior. Similarly, these features also play a significant role in predicting and affecting ION/IOFF current ratio values. Additionally, machine learning is used to determine the optimal design parameters for each figure of merit (FoM) output value. In this context, the models effectively predicted both ION/IOFF current ratios and SS classification, with Naive Bayes achieving an accuracy of 90.8% for ION/IOFF and 92.6% for SS, showcasing the model's robustness in these classification tasks.

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Electro-Thermal Characteristics of Junctionless Nanowire Gate-All-Around Transistors Using Compact Thermal Conductivity Model

Cited by 16 publications

References 41 publications

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

Machine Learning‐Guided Design of 10 nm Junctionless Gate‐All‐Around Metal Oxide Semiconductor Field Effect Transistors for Nanoscaled Digital Circuits

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