Electromagnetic simulation of 3D stacked ICs: Full model vs. S-parameter cascaded based model

Piersanti, Stefano; Paulis, Francesco de; Scogna, Antonio Ciccomancini; Swaminathan, Madhavan; Orlandi, Antonio

doi:10.1109/isemc.2014.6898943

Cited by 4 publications

(1 citation statement)

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“…This approach guarantees signal integrity on high-speed interfaces for PCBs, and advanced simulation tools can be employed to measure performance in terms of gain, loss, and reflection coefficients. Furthermore, importing the S parameter file allows for further analysis, and cascading S parameters enables complete characterization of an interconnection path that includes package and PCB traces [12]. To extract S parameter models from the DDRx PCB, the Sigrity tool was used.…”

Section: Figure 4 Ddrx Interface Test Boardmentioning

confidence: 99%

Package Board Co-Simulation Using Equivalent Circuit Modeling Method for High-Speed System

Saini,

Agarwal

2023

ijmst

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This research paper focuses on the challenges of system-level simulations for high-speed data transfer and the importance of modeling methodology in achieving accurate results. The simulating of PCB alone without considering the package model is not enough. Instead, to ensure optimal system performance, simulating the packages and PCBs together is essential. When simulating the high-speed parallel bus at the PCB level, it's crucial to consider the package model. If the package model is missing, achieving successful results can be challenging. In this paper, a method is proposed for developing a package model that is specific to the nets required for simulation purposes. The paper explores the challenge of simulating high-speed interfaces with a DDRx example that includes an RLC package model. An interconnect model technique is developed to apply the package RLC model through the equivalent circuit modeling method for the high-speed DDRx test board. This solution aims to simplify the co-design process by using simulation and verifying the model with the assistance of an eye diagram of the data bus. The proposed package model reduces jitter in co-simulation and ensures timing compliance for high-speed interfaces.

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Section: Figure 4 Ddrx Interface Test Boardmentioning

confidence: 99%