Electromigration avoidance in analog circuits: two methodologies for current-driven routing

Lienig, Jens; Jerke, Goeran; Adler, T.

doi:10.1109/aspdac.2002.994950

Cited by 20 publications

(15 citation statements)

References 14 publications

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“…As can be seen in Table 2, the wire area and routing area consumption of our approach was less as compared to both edge of mesh graph G currently evaluated edge edge of routing tree R (11) terminal distance in LU current strength in mA the manually adjusted layouts and the strategies presented in [14]. (The approaches in [14] minimize only the routing length and not the overall wire area.)…”

Section: Implementation and Resultsmentioning

confidence: 91%

“…We compared our routing results with layouts that were semi-automatically routed by experienced designers (using Mentor Graphic's IRoute tool) and afterwards manually adjusted for currentdensity. We also compared our results to two approaches presented in [14]. In order to allow a fair comparison, the same detailed router was used in all cases (except for the manually generated designs).…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…(The approaches in [14] minimize only the routing length and not the overall wire area.) The larger routing area of the manual approach is mainly due to the additional area a layout designer will reserve when routing in order to perform wire widening after the topology of the entire net has been laid out (i.e., after all branch currents are known).…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…With the exception of the approaches in [12]- [14], current-driven routing has been applied so far only to layout generation of power and ground nets in digital circuits. In these cases, the generation of power supply interconnect is usually done prior to signal routing in order to achieve a planar (i.e., single layer) implementation.…”

Section: Previous Workmentioning

confidence: 99%

“…The approaches of current-driven signal routing in [12]- [14] are focused on generating current-correct Steiner trees. The proposed current characterization method is very simplified (considering only the minimum and maximum currents at each pin), the Steiner tree generation is based on a connection graph which can only be applied to small problem sizes, and the solutions of [12][13] are restricted to planar layouts.…”

Section: Previous Workmentioning

confidence: 99%

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Current-driven wire planning for electromigration avoidance in analog circuits

Lienig¹,

Jerke

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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-Electromigration due to insufficient wire width can cause the premature failure of a circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, especially with analog circuits. It is therefore an important reliability issue to consider current densities already in the physical design stage. We present a new methodology capable of routing analog multi-terminal signal nets with current-dependent wire widths. It is based on current-driven wire planning which effectively determines all branch currents prior to detailed routing. We also discuss successful applications of our methodology in commercial analog circuit design.

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Section: Implementation and Resultsmentioning

confidence: 91%

Section: Implementation and Resultsmentioning

confidence: 99%

Section: Implementation and Resultsmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%