Electromigration-aware placement for 3D-ICs

Abstract

This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSV's EM objective function is used, providing a computationally efficient way to represent TSV EM other than the finite-element-method (FEM) based simulation. Considering TSV's EM is mutually influenced by neighboring TSVs (due to TSV EM's dependence on TSV-induced thermal mechanical stress) and strongly affected by temperature, iterative optimizations are performed to obtain the optimal TSV's distribution and a desired TSV's temperature. Finally using a compact thermal model and simulated annealing, all logic gates are placed such that the desired temperature profile is reached. Results show that compared with a conventional wirelength centered 3D placer, our design achieves 3.41x longer mean-time-to-failure (MTTF), with only 3% wirelength overhead.

Low-Power Clock Tree Synthesis for 3D-ICs

“…However, since clock tree synthesis is usually performed after the placement of blocks/standard cells/IO pins, the layout whitespace left for TSVs is limited. Moreover, TSVs have larger dimensions than standard cells; for example, a TSV could occupy a 5μm× 5μm to 30μm× 30μm area Lu et al [2016bLu et al [ , 2016c, depending on different fabrication technologies, as compared to less than 1μm× 1μm standard cells at a sub-microtechnology node. In addition, TSVs have to maintain a certain distance from each other, due to mechanical [Jung et al 2012;Lu et al 2016b] and signal integrity [Liu et al 2011] considerations.…”

“…Moreover, TSVs have larger dimensions than standard cells; for example, a TSV could occupy a 5μm× 5μm to 30μm× 30μm area Lu et al [2016bLu et al [ , 2016c, depending on different fabrication technologies, as compared to less than 1μm× 1μm standard cells at a sub-microtechnology node. In addition, TSVs have to maintain a certain distance from each other, due to mechanical [Jung et al 2012;Lu et al 2016b] and signal integrity [Liu et al 2011] considerations. The TSV placement problem is to place the clock TSVs and control TSVs such that each TSV is located inside the layout area and outside other TSVs' keep-out-zones (KOZs) [Lu and Srivastava 2015b;Lu et al 2016c].…”

“…In addition, they are not capable of handling the unique challenge in 3D clock tree design that the shutdown gates can no longer be inserted at every tree edge. As we have explained in Section 1, this is because the TSV placement whitespace is limited during the clock synthesis step, and excessive usage of TSVs brings extra manufacturing cost and raises TSV's reliability concerns Lu et al [2016bLu et al [ , 2016c. Therefore, we aim to generate a 3D abstract clock tree such that the minimum number of shutdown gates is needed while simultaneously reducing the wire length and the power consumption of the clock tree.…”

Numerical Simulation of the Temperature on the Metallization of an Integrated Circuit and its Impact on Interconnect Lifetime

“…The number of vias, the metal density, the metal thickness and the material contribute to a non-uniform temperature distribution [4][5][6]. Such a temperature distribution is of great importance to the IC designer and has to be considered for the performance and reliability evaluation at circuit level [7,8].…”

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

“…Placement of standard cell also plays a significant role in dealing with the electron migration problem due to Through Silicon Vias (TSVs) [6]. In the interest of floorplanning, an initial step to govern the wire length, there is an urge for Electron migration-aware floor plans [7]. Hence, this paper analyzes the Skewed Binary tree (SKB) floorplanning representation, which is based on the Binary tree [8].…”