Electromigration behavior of 60 nm dual damascene Cu interconnects

Abstract

Electromigration ͑EM͒ reliability was investigated for Cu fine lines fabricated using a SiON trench filling process down to 60 nm in linewidth. EM was observed to be dominated by intrinsic failures due to void formation in the line trench. The lifetimes of 60 nm lines were longer than those of 125 nm lines with the standard damascene structure which can be attributed to a distinct via/metal-1 configuration with less process-induced defects at the via interface. The line scaling effect on EM reliability was investigated using three linewidths: 60, 110, and 185 nm. EM lifetimes were found to be similar for different linewidths, consistent with intrinsic failures caused by void formation in the line trench driven by interfacial mass transport. Statistical, multilinked EM test structures demonstrated a monomodal failure distribution for the fine lines, indicating suppression of processing-induced extrinsic defects although processing control on line dimension and geometry remained an issue. The activation energies were found to be around 0.80 eV for both fine lines and standard lines, indicating that interface diffusion dominates mass transport in Cu lines.

Fast recovery of elastic constant in thin films studied by resonant-ultrasound spectroscopy

“…In bulk Cu, activation energies for self diffusion and boundary diffusion are 2.04 eV and 1.08 eV, respectively, 31 and in Cu films, activation energy for electromigration is 0.8-0.91 eV. 32,33 Comparing with them, activation energy for the elastic recovery is significantly smaller, which indicates that the recovery speed is faster.…”

Suppression of Electromigration Early Failure of Cu/Porous Low-kInterconnects Using Dummy Metal

“…Such E a values are slightly larger than those reported previously. [14][15][16] This should be due to the effect of Al addition on Cu diffusion by using the CuAl seed layer. 17) for M2/via2 using SiOCH is larger than that for M1/via1 using SiO 2 at different temperatures, as shown in Fig.…”

Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices

“…Vias connect the metal lines layer by layer and can have structures such as super vias, which skip several layers. Even with scaling down, these interconnects should efficiently deliver external power to individual unit transistors and their characteristics should be maintained or enhanced in terms of power delivery efficiency and reliability while ensuring stable circuit formation [8][9][10]. Since interconnects ultimately serve as pathways for current transmission, it is necessary to minimize the heat generated by Joule heating resulting from current flow [11].…”