While Black's equation for electromigration (EM) in interconnects with n = 1 is rigorously based on the principles of electrotransport, n > 1 is more commonly observed empirically. This deviation is usually attributed to Joule heating. An alternative explanation is suggested by the recent discovery of EM plasticity. To examine this possibility, we have retested samples that had been previously subjected to a predamaging phase of high temperature and current densities to determine whether the loss of median time to failure (MTF) is retained. We find that the predamaged samples exhibit MTFs that are permanently reduced, which is a characteristic of EM plasticity.

Electromigration ͑EM͒ reliability of Cu/low-k interconnects with a conventional preclean-first process, and an advanced barrier-first process has been investigated. Compared with the preclean-first process, extrinsic early failures were not observed for the barrier-first process. This suggests that process-induced defects, which are the most probable cause for early failures, are significantly reduced for the barrier-first process. Transmission electron microscopy observation demonstrated a more uniform and thicker Ta barrier for the barrier-first process than the preclean-first process. This led to a higher ͑jL͒ c product, and prolonged the EM lifetime accordingly. In addition, a predeposited Ta barrier during the barrier-first process protected the mechanically weak low-k dielectrics from plasma etch damage, and a uniform via profile resulted. In contrast, the via opening at the top was found to be larger than that of at the via bottom for the preclean process. The uniform via profile is another advantage of the barrier-first process from the point of view of process control.

Electromigration ͑EM͒ reliability was investigated for Cu fine lines fabricated using a SiON trench filling process down to 60 nm in linewidth. EM was observed to be dominated by intrinsic failures due to void formation in the line trench. The lifetimes of 60 nm lines were longer than those of 125 nm lines with the standard damascene structure which can be attributed to a distinct via/metal-1 configuration with less process-induced defects at the via interface. The line scaling effect on EM reliability was investigated using three linewidths: 60, 110, and 185 nm. EM lifetimes were found to be similar for different linewidths, consistent with intrinsic failures caused by void formation in the line trench driven by interfacial mass transport. Statistical, multilinked EM test structures demonstrated a monomodal failure distribution for the fine lines, indicating suppression of processing-induced extrinsic defects although processing control on line dimension and geometry remained an issue. The activation energies were found to be around 0.80 eV for both fine lines and standard lines, indicating that interface diffusion dominates mass transport in Cu lines.

Stress-induced void formation (SIV) was studied in dual damascene Cu/oxide and Cu/low k interconnects over a temperature range of 140 ∼ 350 °C. Two modes of stressmigration were observed depending on the baking temperature and sample geometry. At lower temperatures (T < 290 °C), voids were formed under the periphery of via connecting to narrow lines. This mode of stressmigration showed a typical behavior of stressmigration with peak damage at 240 °C, and an activation energy (Q) of 0.75 eV for Cu/oxide interconnects. At a higher temperature range (T > 290 °C), voids were found in via bottoms which were connected to wide lines. The rate of high temperature stressmigration increased exponentially with temperature up to 350 °C and did not show a peak at a certain temperature. The activation energy was 1.0 eV for Cu/oxide, 0.86 eV for Cu/OSG, and ∼1.0 eV for Cu/FSG interconnects. The dependence of stressmigration on linewidth, sample geometry, and ILD material is presented in this paper.

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