Electronics beyond nano-scale CMOS

Borkar,

doi:10.1109/dac.2006.229329

Cited by 36 publications

(33 citation statements)

References 3 publications

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“…For example, t (1) denotes the time at the beginning of lifetime (t (1) = 0), and t (N) denotes the time at the beginning of the last (Nth) time-step. At each time step, the control policies decide whether to adjust all, some, or none of the selftuning parameters; if adjustments are made, the corresponding tuning-magnitude is also decided.…”

Section: A Discrete Time-stepsmentioning

confidence: 99%

“…The PMOS threshold voltage may gradually degrade by 50 mV over lifetime (e.g., 7-10 years) under worstcase operating conditions due to traps accumulated at the SiSiO 2 interface. Depending on the design and the operating conditions, this may result in more than 20% speed degradation [1]- [4]. Aging-induced changes in the interface charge depend on the process technology and several dynamic factors: the amount of time elapsed, temperature, workload, and voltage profiles [5]- [7].…”

mentioning

confidence: 99%

“…circuits [1]- [3]. The PMOS threshold voltage may gradually degrade by 50 mV over lifetime (e.g., 7-10 years) under worstcase operating conditions due to traps accumulated at the SiSiO 2 interface.…”

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confidence: 99%

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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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Section: A Discrete Time-stepsmentioning

confidence: 99%

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confidence: 99%

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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…NBTI occurs when a pMOS transistor is negatively biased (V gs = −V DD ) at elevated temperatures and causes the absolute value of the threshold voltage (|V th |) to increase. This shift can increase the delay of the transistor and degrade the circuit speed by about 10%-20% [4].…”

Section: Introductionmentioning

confidence: 99%

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS

Kaffashian

Lotfi

Mafinezhadand

et al. 2011

IEICE Electron. Express

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Abstract:In this paper, the impact of negative bias temperature instability (NBTI) on dynamic logic circuits is analyzed and a design technique for a wide fan-in domino gate based on Genetic Algorithm (GA) optimization is proposed. In this technique, the degraded delay due to NBTI during the lifetime of the circuit is minimized subject to the constraints on area, power consumption and unity noise gain (UNG). The proposed optimization method is implemented in a 65-nm technology for a lifetime of 3 years. In comparison with a typical design, the optimized results show an improvement of more than 21.6% in delay during the circuit lifetime with a negligible change in the power and the UNG. The proposed method has the advantage that it can be used for any desired circuit lifetime with any reasonable constraints on design parameters, just with setting the corresponding parameters in the algorithm.

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“…cuit speed, potentially causing a functional failure [3]. The impact of NBTI on circuit performance has become a key issue with technology scaling [4].…”

Section: Introductionmentioning

confidence: 99%

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang

Chen

Wang

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-1 As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input patterns of circuits. In this paper, we propose a co-simulation flow to study NBTI-induced circuit degradation and leakage power, taking into account the different behaviors between circuit active and standby time. Based on this flow, we evaluate the efficacy of Input Vector Control (IVC) technique on mitigating circuit aging and reducing standby leakage power with experiments on benchmark circuits that are implemented in 90nm, 65nm, and 45nm technology nodes. The IVC technique is proved to be effective to mitigate NBTI-induced circuit degradation, saving up to 56% circuit performance degradation at 65nm technology node, and on average 30% circuit performance degradation across different technology nodes. Meanwhile, IVC technique can save up to 18% of the worst case leakage power. Since leakage power and NBTI-induced circuit degradation have different dependencies on the input patterns, we propose to derive Pareto sets for designers to explore trade-offs between the life-time reliability and leakage power.

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Electronics beyond nano-scale CMOS

Cited by 36 publications

References 3 publications

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

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