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Intel, Hillsboro, OR High-throughput parallel SIMD vector computations are the most performance and power-critical operations in multimedia, graphics and signal processing workloads. An array of SIMD vector processing engines delivers highthroughput short bit-width arithmetic operations on large data sets with orders of magnitude higher energy efficiencies vs. general-purpose cores [1,2]. A reconfigurable 4-way SIMD engine targeted for on-die acceleration of vector processing in power-constrained mobile microprocessors is fabricated in 45nm High-K/Metal-gate CMOS [3]. The accelerator is reconfigured to perform 4-way 16b×16b multiplies, 32b×32b multiply, 4-way 16b additions, 2-way 32b additions and 72b addition with single-cycle throughput and wide dynamic supply voltage range of operation (1.3V to 230mV). A reconfigurable 2×2 tile of signed 2's complement 16b multipliers, with conditional carry gating in the 72b sparse tree adder, dual-supplies for voltage hopping, and finegrained power-gating enables peak energy efficiency of 494GOPS/W (measured at 300mV, 50°C) with a dense layout occupying 0.081mm 2 (Fig. 14.6.7) while achieving: (i) scalable performance up to 2.8GHz, 278mW measured at 1.3V, (ii) fast single-cycle switching between any operating/idle mode, (iii) configuration-dependent power consumption with 41% total power reduction and 6.5× active leakage power savings, (iv) 10× standby leakage reduction during sleep mode, (v) deep subthreshold operation measured at 230mV, 8.8MHz, 87µW, and (vi) compensation for up to 3× performance variation in ultra-low voltage mode.

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