A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS

Abstract

Intel, Hillsboro, OR High-throughput parallel SIMD vector computations are the most performance and power-critical operations in multimedia, graphics and signal processing workloads. An array of SIMD vector processing engines delivers highthroughput short bit-width arithmetic operations on large data sets with orders of magnitude higher energy efficiencies vs. general-purpose cores [1,2]. A reconfigurable 4-way SIMD engine targeted for on-die acceleration of vector processing in power-constrained mobile microprocessors is fabricated in 45nm High-K/Metal-gate CMOS [3]. The accelerator is reconfigured to perform 4-way 16b×16b multiplies, 32b×32b multiply, 4-way 16b additions, 2-way 32b additions and 72b addition with single-cycle throughput and wide dynamic supply voltage range of operation (1.3V to 230mV). A reconfigurable 2×2 tile of signed 2's complement 16b multipliers, with conditional carry gating in the 72b sparse tree adder, dual-supplies for voltage hopping, and finegrained power-gating enables peak energy efficiency of 494GOPS/W (measured at 300mV, 50°C) with a dense layout occupying 0.081mm 2 (Fig. 14.6.7) while achieving: (i) scalable performance up to 2.8GHz, 278mW measured at 1.3V, (ii) fast single-cycle switching between any operating/idle mode, (iii) configuration-dependent power consumption with 41% total power reduction and 6.5× active leakage power savings, (iv) 10× standby leakage reduction during sleep mode, (v) deep subthreshold operation measured at 230mV, 8.8MHz, 87µW, and (vi) compensation for up to 3× performance variation in ultra-low voltage mode.

Cool Mega-Array: A highly energy efficient reconfigurable accelerator

“…Compared with a 41.5-GOPS/ 0.775W (54.8-MOPS/mW) dynamically reconfigurable accelerator [15] and a 3.2-GOPS/50-mW VLIW accelerator(64-MOPS/mW) [13], the CMA-1 has better energy efficiency. Although its energy efficiency is worse compared with that of a 494-GOPS/W SIMD accelerator [14], the reported evaluation result for that accelerator was the peak energy consumption ratio only for the array part when the subthrehold voltage is used, while the sustained performance for actual application programs running on an actual chip is shown here.…”

Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications

“…We propose two architectural mechanisms that complement prior work on variation tolerance in parallel architectures [10]. Decoupled parallel SIMD pipelines extends the work on timing speculation to parallel pipelines, providing tolerance of input-dependent and dynamic variations.…”

“…Additionally, process variations can lead to nonfunctioning pipeline components, which may reduce both yield and performance. Prior approaches addressed this challenge at a coarse granularity, adjusting the supply voltage for entire PEs [10], [17]. Fine-grained approaches, such as voltage interpolation [13], are problematic because of the large overheads involved in providing the numerous supplies necessary for the massive number of low-power computational units.…”

Energy-efficient computing for HPC workloads on heterogeneous manycore chips

“…High energy efficiency of operation at low voltages has been established for 65, 45, 32, 22 nm technologies [7,22,28,29]. Kaul et al [27,29] show that as the supply voltage of the transistor is reduced, the energy efficiency increases, and is maximum near the threshold voltage of the transistor.…”