Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications

Abstract

Abstract-While Moore's law scaling continues to double transistor density every technology generation, supply voltage reduction has essentially stopped, increasing both power density and total energy consumed in conventional microprocessors. Therefore, future processors will require an architecture that can: a) take advantage of the massive amount of transistors that will be available; and b) operate these transistors in the near-threshold supply domain, thereby achieving near optimal energy/computation by balancing the leakage and dynamic energy consumption. Unfortunately, this optimality is typically achieved while running at very low frequencies (i.e. 0.1 − 10MHz ) and with only one computation executing per cycle, such that performance is limited. Further, near-threshold designs suffer from severe process variability that can introduce extremely large delay variations. In this paper, we propose a near energy-optimal, stream processor family that relies on massively parallel, near-threshold VLSI circuits and interconnect, incorporating cooperative circuit/architecture techniques to tolerate the expected large delay variations. Initial estimations from circuit simulations show that it is possible to achieve greater than 1 Giga-Operations per second (1GOP/s) with less than 1mW total power consumption, enabling a new class of energy-constrained, high-throughput computing applications.

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

“…Errors introduced by process variation appear in the form of differences in delay for driven signals and input offset and delay for receiver circuits. However, because these errors are generally static in nature they can potentially be mitigated by embedded measurement and calibration circuits [23], localized adaptive body biasing and voltage scaling [38], or device and block sparing [39].…”

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

“…Research has shown that minimum energy is typically achieved when V dd enters the near/sub-threshold region, where about a 10× reduction in energy per computation is achievable [7]. In these cases, the impact of static variations become much more extreme and can be very difficult to predict in large CMOS dies [8].…”

“…These slower speeds lead designers to push sub-threshold processors to a more parallel approach. For example, in [8] the authors use multiple execution lanes to regain the throughput lost by the increased delays of sub-threshold operation. The following subsections will discuss the viability of the techniques under review to operate in the sub-threshold region.…”

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures

“…We explore the tradeoffs associated with timing speculation in the context of SIMD designs, and build on our earlier work [13], to develop and evaluate SIMD-and GPU-specific extensions to the timing speculation technique. In our initial work, we observed that naively applying timing speculation to a SIMD pipeline may perform poorly.…”