Cool Mega-Array: A highly energy efficient reconfigurable accelerator

Abstract

A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm 2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported.

The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator

“…Compared with a 41.5-GOPS/ 0.775W (54.8-MOPS/mW) dynamically reconfigurable accelerator [7] and a 3.2-GOPS/50-mW VLIW accelerator (64-MOPS/mW) [4], the CMA-1 has better energy efficiency. Detail analysis of performance and energy consumption of CMA-1 is shown in [1].…”

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing

“…For example, in ADRES [2] the power overhead of the VLIW processor used to handle the data memory access is up to 20%. In CMA [39] the host CPU feeds the data into the PEs through a shared fetch register (FR) file. This is very inefficient in terms of flexibility.…”

Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms

“…Both of them employ multiple cores with the objective of distributing heterogeneous tasks to each core to save power, not to reach a significant amount of speedup with respect to single-core solutions. Past work on integration of low-power microcontrollers with accelerators has mainly concentrated on coupling with special-purpose computing devices such as specialized DSPs [23] [24], ASICs [5] [25], or reconfigurable computing fabrics [26]. Contrarily to the model we propose, none of these platforms can be considered fully programmable in a general-purpose sense, and no one supports a full offload of code from a host.…”