Eliminated common-mode voltage pulsewidth modulation to reduce output current ripple for multilevel inverters

Nguyen, Tam-Khanh Tu; Nguyen, Nho-Van; Prasad, Nadipuram R.

doi:10.1109/tpel.2015.2489560

Cited by 86 publications

(37 citation statements)

References 38 publications

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“…Mode 2: When N is odd, there is a reference vector at the center of the sector, where θ = π/6. Except for the reference vector at θ = π/6, the switching sequences of other reference vectors V r1~V r2 and V r4~V r5 are the same as Mode 1, which is V 0 ↔ V 7 (V 8 ) ↔ V 13 . The sequence of the reference vector is…”

Section: Principlementioning

confidence: 99%

“…To sum up, how to reduce the switching loss and amplitude of common mode voltage is a problem that must be considered in the high power motor system. At present, domestic and overseas scholars have carried out extensive and in-depth research on the problems of high switching loss [6][7][8][9][10] and high common mode voltage [11][12][13][14][15] of multilevel inverters, and have made a series of achievements. In terms of switching loss reduction, in Reference [6], a closed-loop control strategy based on carrier modulation is proposed, in which the clamping region is inserted in every half fundamental period to reduce switching loss.…”

Section: Introductionmentioning

confidence: 99%

“…But due to the degree of freedom used in the switching state setting of the strategy, the THD of the output current and voltage of the inverter is greatly increased compared to the traditional strategy. In Reference [13], considering the shortcomings of the three zero common mode voltage vector in the output waveform quality of the inverter, a modulation strategy for improving the output waveform quality is proposed based on the degree of freedom set for the switching state, but the principle of the three zero common mode voltage vector must be satisfied. Additionally, the design and selection rules of the optimal switch sequence are obtained through the analysis of the current ripple.…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, the design and selection rules of the optimal switch sequence are obtained through the analysis of the current ripple. Based on the analysis of Reference [13], Reference [14] proposes a double zero vector synthesis sequence method, which can reduce the output current ripple while ensuring the zero common mode voltage amplitude of the inverter. In Reference [15], a method of reducing switching loss by adjusting the position of the zero vector in the sampling period is proposed, and the basic vector synthesis switching sequence with small common mode voltage amplitude is selected.…”

Section: Introductionmentioning

confidence: 99%

“…However, the calculation process of this method is complex, and the strategy is essentially a continuous modulation strategy, the switching loss can be further reduced. However, it must be noted that References [12][13][14][15] all adopt the synthesis method of the non-nearest three vector, the ripple, and THD value of output waveform of the inverter will go up, especially in the low modulation index.…”

Section: Introductionmentioning

confidence: 99%

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Improved Synchronized Space Vector PWM Strategy for Three-Level Inverter at Low Modulation Index

et al. 2019

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Aimed at reducing the switching loss and common-mode voltage amplitude of high-power medium-voltage three-level inverter under low modulation index conditions, an improved synchronous space vector PWM strategy is proposed in this paper. The switching times in each fundamental period are reduced by the re-division of small regions and the full use of the redundant switching state. The sum of switching algebra is introduced as an evaluation index and the switching state with the minimum value of the sum of switching algebra are adopted. Then, the common mode voltage amplitude is reduced. The theoretical analysis and experimental results show that the improved modulation strategy proposed in this paper can effectively reduce the switching loss and common-mode voltage amplitude of the inverter under the condition of the low modulation index. Moreover, the neutral-point voltage ripple is also reduced simultaneously.

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Section: Principlementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Improved Synchronized Space Vector PWM Strategy for Three-Level Inverter at Low Modulation Index

et al. 2019

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A hybrid space vector modulation for the near‐zero common‐mode voltage and common‐mode current mitigation in diode‐clamped multilevel‐inverter‐fed induction motor drive

Selvaperumal

Kirubakaran

Bharatiraja

2020

Int Trans Electr Energ Syst

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Three-level diode-clamped (DC) multilevel inverters (MLIs) and its pulse width modulations (PWMs) are studied widely due to its extensive rewards in industrial drives. These modulation schemes are mainly concentrated to mitigate the zero common-mode (CM) voltage (CMV) and CM current (CMC). Unfortunately, although achieving near-zero CMV, these conventional methods are inadequate to maintain the DC-link low-frequency neutral point voltage oscillations. Hence, bulky DC-link capacitors are used in DC-MLIs. In this article, a full CM voltage eliminated the modified space vector modulation (SVM) method by combining the three medium switching vectors (M 3 V) with one zero vector and two medium switching vectors (M 2 ZV) is proposed. The hybridization of M 3 V + M 2 ZV uses the simple digital circuit to combine M 3 V and M 2 ZV, which creates near-zero CMV and CMC with an improved DC-link capacitor voltage balancing. The studies on the creation and effects of CMV and CMC are presented in detailed. Compared with the early reported full CMV elimination research works, the proposed method maintains the DC-link capacitors voltage balancing without compromising the complete elimination of the CMV. Depending on the reference vector modulation indices and DClink capacitor voltages, the proposed method uses the mixture of both the M 3 V and M 2 ZV switching states. The nominated switching vectors keep the CMV and CMC near to zero with capacitor voltage fluctuation with 1.8%. List of Symbols and Abbreviations: C b , bearing capacitance; C rs , rotor to stator frame parasitic capacitance; C wf , parasitic capacitive; C wr , parasitic capacitance between stator and rotor winding; C ws , parasitic capacitance in stator winding and frame; E SW , switching energy matrix; f o , fundamental frequency; f s , switching frequency; i b , bearing current; M a , modulations index; P sw , switching losses; S f , switching function; T s , switching time; V ao , V bo , and V co , inverter a, b, and c pole voltages; V b , bearing voltage; V C1 and V C2 , DC-link capacitors; V CM , common-mode voltage; V DC , DC-link

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Common-Mode Voltage Elimination of Three-Phase Multilevel Voltage Source Inverter by Means of Quarter-Wave-Symmetric Space Vector PWM Approach

Lopatkin

2021

Smart Innovation, Systems and Technologies

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The new common-mode-voltage-eliminating (CMVE) space vector PWM algorithm for three-phase multilevel voltage source inverter (MLVSI) of any arbitrary topology with any arbitrary number of generated equal voltage levels is proposed. This technique employs all the approaches and attributes of the recently offered quarter-wave-symmetric space vector PWM algorithm but, unlike the latter, operates with quantities in the coordinate frame of the relative values of the MLVSI phase load voltages, referred to the three-phase load common star point (phase-to-neutral load voltages). The applied MLVSI voltages space vectors are the selected space vectors which produce the zero value of the three-phase common-mode voltage, understood as the voltage across the neutral point of the load and the inverter system ground point. Similar to the baseline algorithm, intended for shaping the high-quality MLVSI output voltages and currents, the new CMVE algorithm generates enough high-quality output power, thanks to keeping the quarter-wave symmetry of the star (phase-to-neutral) and delta (phase-to-phase) voltages. The dependences of the THD and low-order weighted THDs values on the phase voltage amplitude modulation index are obtained by PSIM-simulation for the three low, multiple of 6, values of frequency modulation index.

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Eliminated common-mode voltage pulsewidth modulation to reduce output current ripple for multilevel inverters

Cited by 86 publications

References 38 publications

Improved Synchronized Space Vector PWM Strategy for Three-Level Inverter at Low Modulation Index

Improved Synchronized Space Vector PWM Strategy for Three-Level Inverter at Low Modulation Index

A hybrid space vector modulation for the near‐zero common‐mode voltage and common‐mode current mitigation in diode‐clamped multilevel‐inverter‐fed induction motor drive

Common-Mode Voltage Elimination of Three-Phase Multilevel Voltage Source Inverter by Means of Quarter-Wave-Symmetric Space Vector PWM Approach

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