Elimination of Single Event Latchup in 90nm SRAM Technologies

Puchner, H.; Kapre, R.; Sharifzadeh, Sahar; Majjiga, J.; Ren, Chao; Radaelli, D.; Wong, S.

doi:10.1109/relphy.2006.251342

Cited by 15 publications

(11 citation statements)

References 2 publications

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“…In this thesis, it is shown that a single NMOSFET built in a triple well collects more charge than an NMOSFET built in a dual well. This agrees with the observation of increased SER by Puchner et al [3] and Gasiot et al [12]. Also, it is seen that increasing the p-well contact size reduces charge collection, which agrees with the observations in [3] and [12].…”

Section: Overview Of Previous Worksupporting

confidence: 92%

“…This agrees with the observation of increased SER by Puchner et al [3] and Gasiot et al [12]. Also, it is seen that increasing the p-well contact size reduces charge collection, which agrees with the observations in [3] and [12]. It can be postulated from the mechanisms of charge collection proposed in the thesis that, in a large well, placing p-well contacts frequently helps in the recovery of the system from the upset.…”

Section: Overview Of Previous Worksupporting

confidence: 90%

“…In a recent publication on triple wells, an increase in SER was shown with alpha and neutron testing on 65 nm SRAMs [12]. It was claimed that with an increase in p-well ties, the bipolar charge collection for triple-well devices could be reduced.…”

Section: Overview Of Previous Workmentioning

confidence: 99%

See 2 more Smart Citations

Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Roy

Witulski

Schrimpf

et al. 2008

IEEE Trans. Nucl. Sci.

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Section: Overview Of Previous Worksupporting

confidence: 92%

Section: Overview Of Previous Worksupporting

confidence: 90%

See 1 more Smart Citation

Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Roy

Witulski

Schrimpf

et al. 2008

IEEE Trans. Nucl. Sci.

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“…Adding a current-limiting device to power line can mitigate SEL by reducing the power supply current in the case of a latchup event [2] [3]. This method involves additional area for the current limiting device, and an SRAM macro must be redesigned.…”

Section: Introductionmentioning

confidence: 99%

Preventing single event latchup with deep P-well on P-substrate

Uemura

Kato

Tanabe

et al. 2014

2014 IEEE International Reliability Physics Symposium

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Abstract-We propose a method that prevents single event latchup (SEL) using deep P-well on P-substrate. To confirm the effectiveness of the proposed method, SEL and single event upset (SEU) are evaluated for three well configurations; double-well, ordinary triple-well and the proposed deep P-well on P-substrate. Neutron irradiation test shows that the proposed method achieves SEL prevention without SEU increase.

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“…An example of the deep n well and deep p well implementations is shown in Figure 2. Triple wells have been shown to reduce SEL 8,9 in some situations. The inclusion of a triple well option, which is common in processes of ≤ 0.18 µm, originally had the purpose of allowing back-biasing and noise isolation in analogue and Radio Frequency (RF) circuits.…”

mentioning

confidence: 99%

Single event effects in 0.18μm CMOS image sensors

et al. 2016

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CMOS image sensors are widely used on Earth and are becoming increasingly favourable for use in space. Advantages, such as low power consumption, and ever-improving imaging peformance make CMOS an attractive option. The ability to integrate camera functions on-chip, such as biasing and sequencing, simplifies designing with CMOS sensors and can improve system reliablity. One potential disadvantage to the use of CMOS is the possibility of single event effects, such as single event latchup (SEL), which can cause malfunctions or even permanent destruction of the sensor. These single event effects occur in the space environment due to the high levels of radiation incident on the sensor. This work investigates the ocurrence of SEL in CMOS image sensors subjected to heavy-ion irradiation. Three devices are investigated, two of which have triple-well doping implants. The resulting latchup cross-sections are presented. It is shown that using a deep p well on 18 µm epitaxial silicon increases the radiation hardness of the sensor against latchup. The linear energy transfer (LET) threshold for latchup is increased when using this configuration. Our findings suggest deep p wells can be used to increase the radiation tollerance of CMOS image sensors for use in future space missions.

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Elimination of Single Event Latchup in 90nm SRAM Technologies

Cited by 15 publications

References 2 publications

Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Preventing single event latchup with deep P-well on P-substrate

Single event effects in 0.18μm CMOS image sensors

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