Elimination of Vmin failures in 0.15um logic process

Abstract

A significant increase in Vmin failures was observed with device shrinkage. These Vmin failures were observed to be random on wafer and were highly correlated to IDDQ and Delta IDDQ failures. A strong correlation of Vmin failures to STI depth was found. Fault isolation showed that the root cause of our Vmin failures was due to stress related dislocations. Structural and electrical characterizations were used to confirm the proposed root cause mechanism. This paper presents a simple and cost effective method in resolving high Vmin failure rate in production devices. With the new process, a significant yield gain was achieved.