A significant increase in Vmin failures was observed with device shrinkage. These Vmin failures were observed to be random on wafer and were highly correlated to IDDQ and Delta IDDQ failures. A strong correlation of Vmin failures to STI depth was found. Fault isolation showed that the root cause of our Vmin failures was due to stress related dislocations. Structural and electrical characterizations were used to confirm the proposed root cause mechanism. This paper presents a simple and cost effective method in resolving high Vmin failure rate in production devices. With the new process, a significant yield gain was achieved.

Gate oxide integrity issues could be a challenge when integrating high voltage devices (defined by thick gate oxide) into an increasingly advanced logic process. Localized TDDB failures due to STI corner induced gate oxide thinning at the wafer edge were found to be related to the pump port in the STI etch chamber. We showed that STI top corner rounding can be optimized by creating a "passivation-dominant" etch. Mechanisms of "double-hump" STI corner formation, designdependent STI corner profiles and wet clean optimizations to achieve TDDB requirements were discussed. The new process showed significant yield enhancement in a state-of-the-art NXP Power Management Unit from DC/DC converter performance improvements.