Embedded Architecture Description Language

Li, Juncao; Pilkington, Nicholas T.; Xie, Fei; Liu, Qiang

doi:10.1109/compsac.2008.121

Cited by 6 publications

(6 citation statements)

References 25 publications

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“…There has been lots of research on formalizing interface semantics, such as I/O automata by Lynch, et al [7], interface automata by De Alfaro, et al [8], and ω-automata used in component-based design of embedded systems by Li, et al [9]. Kroening, et al [10] have used SystemC [11] to specify HW/SW interface designs.…”

Section: Related Workmentioning

confidence: 99%

Formalizing hardware/software interface specifications

Xie

Ball

et al. 2011

2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011)

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Abstract-Software drivers are usually developed after hardware devices become available. This dependency can induce a long product cycle. Although co-simulation and co-verification techniques have been utilized to facilitate the driver development, Hardware/Software (HW/SW) interface models, as the test harnesses, are often challenging to specify. Such interface models should have formal semantics, be efficient for testing, and cover all HW/SW behaviors described by HW/SW interface protocols. We present an approach to formalizing HW/SW interface specifications, where we propose a semantic model, relative atomicity, to capture the concurrency model in HW/SW interfaces; demonstrate our approach via a realistic example; elaborate on how we have utilized this approach in device/driver development process; and discuss criteria for evaluating our formal specifications. We have detected fifteen issues in four English specifications. Furthermore, our formal specifications are readily useful as the test harnesses for co-verification, which has discovered twelve real bugs in five industrial driver programs.

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Section: Related Workmentioning

confidence: 99%

Formalizing hardware/software interface specifications

Xie

Ball

et al. 2011

2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011)

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“…Space limitation prohibits an in-depth description of patterns and other advanced features of EADL (refer to [9]). …”

Section: Figure 2 Component Examplementioning

confidence: 99%

“…We have developed an Embedded System Integrated Development Environment (ESIDE), which is based on the Embedded Architecture Description Language (EADL) [9]. The key features of ESIDE are as follows:…”

Section: Introductionmentioning

confidence: 99%

ESIDE: An Integrated Development Environment for Component-Based Embedded Systems

Pilkington

Xie

2009

2009 33rd Annual IEEE International Computer Software and Applications Conference

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“…In the same fashion, it makes sense to build verification components that can be reused in multiple chip design projects. However, the idea of reusable verification blocks is more recent than reusable design blocks [1,[6][7][8][9][10][11]22]. Many ASIC designs are evolutions or derivatives of earlier designs.…”

Section: Introductionmentioning

confidence: 99%

Verification Components Reuse

Sagahyroon¹,

Lakkaraj²,

Karunaratne³

2012

JCP

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Design verification of ASICs is often approached in an ad-hoc manner without the care, planning and scrutiny that usually accompanies a typical design effort. As the complexity of ASIC design increases, it is expected that the complexity of verification environments of such designs will increase as well. To reduce development time and effort, design reuse or the use of design blocks from one project to the next is often practiced. In this work, and in an effort to improve the efficiency of design verification efforts, we propose a methodology that advocates verification components reuse. The proposed approach utilizes a bottom-up, functional design verification strategy that encourages building and using modular and reusable verification components. The design of the hardware for the IEEE Ten Gigabit Ethernet standard is used to illustrate the feasibility and applicability of this approach.

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Embedded Architecture Description Language

Abstract: In the state-of-the-art hardware/software (HW/SW) component-based co-design, cosimulation, co-verification, and system synthesis.

Cited by 6 publications

References 25 publications

Formalizing hardware/software interface specifications

Formalizing hardware/software interface specifications

ESIDE: An Integrated Development Environment for Component-Based Embedded Systems

Verification Components Reuse

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