2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.
DOI: 10.1109/vlsit.2006.1705221
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Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Abstract: Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different β-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm Fin width, 90 nm channel height and 20 nm gate length at V dd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date.A higher beta ratio (β > 2.0) in FinFET SRAM cell will be also achieved by tuning the eff… Show more

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Cited by 43 publications
(23 citation statements)
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“…As new designs use transistors with minimum size, the device variations have a large impact on cell variability. In this paper, we modeled process variations as Gaussian distribution with 3 V equal to 10% on the size and threshold voltage of transistors [22]. The simulations are performed by applying 1000 iterations of Monte Carlo simulation on SRAM cell during read operation.…”
Section: B Process Variations and Cell Failure Ratesmentioning
confidence: 99%
“…As new designs use transistors with minimum size, the device variations have a large impact on cell variability. In this paper, we modeled process variations as Gaussian distribution with 3 V equal to 10% on the size and threshold voltage of transistors [22]. The simulations are performed by applying 1000 iterations of Monte Carlo simulation on SRAM cell during read operation.…”
Section: B Process Variations and Cell Failure Ratesmentioning
confidence: 99%
“…However, it is very difficult to replace all transistors by FinFETs. Recently, both planar FET peripheral circuit and FinFET SRAM were fabricated on a bulk Si substrate in order to introduce FinFET to LSI fabrication early and prove that logic and SRAM FETs are unaffected by integration [5]. The fabrication process is shown in …”
Section: Gate Stackfor Finfetmentioning
confidence: 99%
“…19(b)). fin height variation [5] become a prospective device for future SoC applications. As future works, the advantage of no dopant fluctuation in FinFET SRAM hardware should be demonstrated.…”
Section: E Fin Height Tuning Techniquefor F-ratio Controlmentioning
confidence: 99%
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“…For example, the static noise margin of the FinFET implementation of a static RAM cell is shown to be much better than its bulk CMOS implementation [3]. However, FinFETs still face intradie and interdie process variations in a number of parameters, such as gate length, fin thickness, work function, and oxide thickness, all of which have an impact on the delay and power characteristics of FinFET logic gates, and thus the die yield.…”
mentioning
confidence: 99%