FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Abstract

Continued scaling of bulk CMOS technology is facing formidable challenges. FinFETs, with better control of short-channel effects, offer a promising alternative for the 22-nm technology node and beyond. However, FinFETs still suffer from process, voltage, and temperature (PVT) variations. Thus, to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis. In this paper, using an existing SSTA algorithm as a foundation, we analyze silicon-on-insulator FinFET circuits in various new ways: 1) basing the analysis on accurate device simulation of the logic library; 2) considering voltage and temperature variations, in addition to process variations; 3) deriving accurate timing and leakage macromodels; and 4) investigating the impact of PVT variations on delay/leakage distributions at the circuit level. We propose a simplified timing model that greatly reduces the computational complexity without giving rise to any convergence issues. The timing model has an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared with accurate quasi-Monte Carlo simulations. We evaluate the performance of our SSTA algorithm with respect to Monte Carlo simulation, and extend the algorithm to enable statistical leakage and dynamic power analysis as well. We investigate the impact of PVT variations on delay/power distributions at the circuit level. We show that deterministic optimization methods can optimize both the mean and variance of circuit delay/power distributions, and even the ratio of standard deviation to mean in some cases. Finally, we show that FinFET circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

“…FinPrin [35] is a tool for statistically analyzing the delay and power consumption of FinFET circuits. It has been validated against Monte Carlo simulations, incurring <5% testing error.…”

“…However, this is not very accurate. In McPAT-PVT, the macromodels are derived from synthesis using Design Compiler [49] and statistical analysis using FinPrin [35] based on device-simulated standard cells and with place-and-route information incorporated. Thus, it is much more accurate.…”

“…Although dynamic power varies little with temperature for FinFET implementations [35], leakage power is exponentially dependent on temperature. Hence, leakage power should be evaluated at a self-consistent temperature at which leakage power and temperature are in equilibrium [28].…”

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

“…Whereas most of the attention has been paid to timing analysis, a few researchers have also investigated power variations under the effect of PVT variations [16]- [18]. Mukhopadhyay and Roy [16] present an analytical model to estimate leakage variations due to gate tunneling and reverse-biased source/drain junction band-to-band tunneling, as well as due to correlations among these components.…”

“…Chang and Sapatnekar [17] propose a method that treats leakage as a lognormal random variable (RV). While the above methods evaluate CMOS circuits, Yang and Jha [18] present a FinFET logic library that can be used to model timing, leakage power, and dynamic power distributions, based on augmentation of the framework presented in [10], [11], and [17].…”