In this paper, the emission features of singly-charged and doubly-charged projectile fragments emitted in interactions of [Formula: see text] with emulsion at 1[Formula: see text]A[Formula: see text]GeV are studied. We have also observed the dependence of the singly-charged and doubly-charged projectile fragments on the interaction with different target groups of the emulsion detectors. The multi-source model can characterize the projectile fragments, and each source provides an exponential distribution, according to our calculations. The present observation shows that the emission features of the singly-charged and doubly-charged projectile fragments are independent on the interaction with different target groups of the emulsion.

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Herein, we report a method to estimate the thermodynamic potentials of electrochemical reactions at different temperatures. We use a two-term Taylor series approximation of thermodynamic potential as a function of temperature, and we calculate the temperature sensitivity for a family of twenty seven known half reactions. We further analyze pairs of cathode and anode half-cells to pinpoint optimal voltage matches and discuss implications of changes in temperature on overall cell voltages. Using these observations, we look forward to increased interest in temperature and idealized half-reaction pairing as experimental choices for the optimization of electrochemical processes.

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Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.