Embedded DRAM built in self test and methodology for test insertion

Jakobsen, P.; Dreibelbis, J.; Pomichter, G.; Anand, D.; Barth, J.; Nelms, M.; Leach, Janice; Belansek, G.

doi:10.1109/test.2001.966722

Cited by 17 publications

(11 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…TABLE IV gives a comparison of key issues in terms of supported algorithms, full-speed tests, instruction size and the area overhead. One micro-code based solution [1] was proposed to support various test algorithms for testing the eDRAM macro. It uses an area-consuming storage to load the instruction.…”

Section: Experimental Results and Comparisonsmentioning

confidence: 99%

“…In general, the design of P-MBIST can be classified into two main types: micro-code based P-MBIST [1][2][3] and singleinstruction based P-MBIST [4]. Typically, the micro-code based solution defines the instruction format to support the operations of the selected memory test algorithms and the test patterns are loaded on the internal program memory.…”

Section: Introductionmentioning

confidence: 99%

“…A microcode-based P-MBIST [1] was proposed to test the eDRAM macro. It supports specific test algorithms based on a customized processor.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Single-instruction based programmable memory BIST for testing embedded DRAM

Lin

Wang

et al. 2009

2009 International Symposium on VLSI Design, Automation and Test

View full text Add to dashboard Cite

With the increasing functionalities in modern SoC design, the need for dense embedded memory is growing. The test issue for this high density embedded DRAM (eDRAM) macro in a complex integration environment is becoming an important issue. In this work, we propose a single-instruction based programmable memory BIST for testing an eDRAM macro. Based on our BIST design, the supported memory testing algorithms are classified into five groups. Moreover, a compact instruction is proposed to encode the operation of each group and a two-level address generator is adopted to produce all the required addressing indexes. The proposed architecture provides a better design tradeoff in terms of the area overhead and the programmability compared with the existing work.

show abstract

Section: Experimental Results and Comparisonsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Single-instruction based programmable memory BIST for testing embedded DRAM

Lin

Wang

et al. 2009

2009 International Symposium on VLSI Design, Automation and Test

View full text Add to dashboard Cite

show abstract

“…The programmable controllers required about 4x to 5x the area of a static BIST controller based on MARCH algorithms. Microcode-based controllers have also been proposed by Jakobsen et al [JDP+01], Appello et al [ABF+03]. A CPU-based controller uses an on-chip special-purpose processor for the generation of test sequences; such controllers are proposed in [ZS+03].…”

Section: Previous Workmentioning

confidence: 99%

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Kokrady

Ravikumar

Chandrachoodan

2008

2008 17th Asian Test Symposium

View full text Add to dashboard Cite

Debugging memory test failures in a system-on-chip design is becoming difficult due to the growing number and sizes of the embedded memories. Low-complexity marching tests, which are ideally suited for production testing, are insufficient for debug and diagnostics. On-chip support for multiple memory test algorithms can be prohibitively expensive. Moreover, memory test engineers would like the flexibility to make small changes to the test sequence. Runtime programmability can be provided through the use of programmable finite state machines and/or microcode in the BIST controllers. Since such controllers have higher area requirement, it is difficult to employ multiple controllers and distribute them geographically on the chip. Therefore, the BIST controller can become a routing hot-spot. Existing memory BIST insertion flows operate on a post-synthesis net-list and ignore the constraints that will be posed by the physical design step that will follow. These constraints include routing congestion and interconnect timing. Similarly, the synthesis of the BIST logic must also address area, test application time and test power constraints. In this paper, we formulate the problem of programmable memory BIST synthesis as an optimization problem and describe an implementation. Results show upto 3X improvement in area and wirelength for industrial designs when a layout-aware flow is used as opposed to manual BIST implementation.

show abstract

“…This can reduce the re-design cost. The microcode programmable BIST uses a ROM to store often used test algorithms and a scannable ROM to support the in-field programmability of test algorithms [5], [12]. This approach provides high flexibility of in-field programmability and metal-mask programmability, but it needs high area cost.…”

Section: Introductionmentioning

confidence: 99%

A hybrid built-in self-test scheme for DRAMs

Yang

et al. 2015

VLSI Design, Automation and Test(VLSI-Dat)

View full text Add to dashboard Cite

This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

show abstract

Embedded DRAM built in self test and methodology for test insertion

Cited by 17 publications

References 8 publications

Single-instruction based programmable memory BIST for testing embedded DRAM

Single-instruction based programmable memory BIST for testing embedded DRAM

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

A hybrid built-in self-test scheme for DRAMs

Contact Info

Product

Resources

About