Embedded Multi‐die Interconnect Bridge (EMIB)

Mahajan, Ravi; Sankman, Robert; Aygün, Kemal; Qian, Zhiguo; Dhall, Ashish; Rosch, Jonathan L.; Mallik, Debendra; Salama, Islam A.

doi:10.1002/9781119313991.ch23

Cited by 8 publications

(1 citation statement)

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“…These trends in FPGA architecture along with with recent advances in 2.5D and 3D chip integration technologies [3], [21] have resulted in the emergence of a new class of beyond-FPGA reconfigurable devices that combine the flexibility of FPGAs, the efficiency of hard NoCs for data steering, and the high-performance of specialized accelerator blocks. Our work focuses on building tools that enable rapid architecture exploration for these complex devices and also facilitate application re-design when migrating from conventional FP-GAs to novel RADs.…”

Section: Background and Related Work A The Emergence Of Beyond-fpga Radsmentioning

confidence: 99%

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

2022

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In recent years, field-programmable gate arrays (FPGAs) have been increasingly deployed in datacenters as programmable accelerators that can offer software-like flexibility and custom-hardwarelike efficiency for key datacenter workloads. To improve the efficiency of FPGAs for these new datacenter use cases and data-intensive applications, a new class of reconfigurable acceleration devices (RADs) is emerging. In these devices, the FPGA fine-grained reconfigurable fabric is a component of a bigger monolithic or multi-die system-in-package that can incorporate general-purpose software-programmable cores, domain-specialized accelerator blocks, and high-performance networks-on-chip (NoCs) for efficient communication between these system components. The integration of all these components in a RAD results in a huge design space and requires re-thinking the implementation of applications that need to be migrated from conventional FPGAs to these novel devices. In this work, we introduce RAD-Sim, an architecture simulator that allows rapid design space exploration for RADs and facilitates the study of complex interactions between their various components. We also present a case study that highlights the utility of RAD-Sim in re-designing applications for these novel RADs by mapping a state-of-the-art deep learning (DL) inference FPGA overlay to different RAD instances. Our case study illustrates how RAD-Sim can capture a wide variety of reconfigurable architectures, from conventional FPGAs to devices augmented with hard NoCs, specialized matrix-vector blocks, and 3D-stacked multi-die devices. In addition, we show that our tool can help architects evaluate the effect of specific RAD architecture parameters on end-to-end workload performance. Through RAD-Sim, we also show that novel RADs can potentially achieve 2.6× better performance on average compared to conventional FPGAs in the key DL application domain.INDEX TERMS deep learning, field-programmable gate arrays, hardware acceleration, network-on-chip, reconfigurable computing

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Section: Background and Related Work A The Emergence Of Beyond-fpga Radsmentioning

confidence: 99%

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

2022

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Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

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