Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA

Wiersema, Tobias; Bockhorn, Ame; Platzner, Marco

doi:10.1109/reconfig.2014.7032514

Cited by 16 publications

(6 citation statements)

References 12 publications

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“…FPGA compilation can be further improved with a virtualization layer. Overlay-based virtualization [7,42,48,49,52,95] abstracts away target-specific details and enables fast compilation and lower deployment latency. The approach reduces utilization and performance.…”

Section: Related Workmentioning

confidence: 99%

Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in data centers. Applications in data centers run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software at sub-clock-tick granularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is available today. We use Synergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3 − 4× of unvirtualized performance, and incur a modest increase in FPGA fabric utilization. CCS CONCEPTS• Hardware → Hardware description languages and compilation; Reconfigurable logic and FPGAs; • Software and its engineering → Compilers; Operating systems.

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Section: Related Workmentioning

confidence: 99%

Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

View full text Add to dashboard Cite

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“…The first is to create FPGA designs that are independent of the specific structures on a particular FPGA and therefore to make designs portable, or, in other words, able to be mapped to FPGAs from different vendors and to different devices from the same vendor. This class of FPGA overlay designs [5,41] creates basic FPGA structures, such as Look-Up Tables (LUTs) and routing, built on top of those provided in silicon on the target FPGA chip. We are using an FPGA overlay for the second purpose; namely, to reduce the amount of time to translate a design to an FPGA implementation.…”

Section: Related Workmentioning

confidence: 99%

“…To address these challenges, we propose a generic, reconfigurable implementation of SFE as a coarse-grained FPGA overlay architecture. As FPGAs have become more dense and capable of holding a large number of gate equivalents, there has been an increased interest in FPGA overlay architectures [5,13,14,[16][17][18]41]. An FPGA overlay consists of two parts: (1) a circuit design implemented on the FPGA fabric using the usual design flow, and (2) a user circuit mapped onto that overlay circuit.…”

Section: Introductionmentioning

confidence: 99%

Secure Function Evaluation Using an FPGA Overlay Architecture

Fang

Ioannidis

Leeser

2017

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Secure Function Evaluation (SFE) has received considerable attention recently due to the massive collection and mining of personal data over the Internet, but large computational costs still render it impractical. In this paper, we leverage hardware acceleration to tackle the scalability and efficiency challenges inherent in SFE. To that end, we propose a generic, reconfigurable implementation of SFE as a coarsegrained FPGA overlay architecture. Contrary to tailored approaches that are tied to the execution of a specific SFE structure, and require full reprogramming of an FPGA with each new execution, our design allows repurposing an FPGA to evaluate different SFE tasks without the need for reprogramming. Our implementation shows orders of magnitude improvement over a software package for evaluating garbled circuits, and demonstrates that the circuit being evaluated can change with almost no overhead.

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“…Fine-grained overlays are FPGA-like architectures [17,[19][20][21] , where REs are composed of fine-grain reconfigurable elements, such as Configurable Logic Blocks (CLBs). Fig.…”

Section: Fine-grained Overlaysmentioning

confidence: 99%

“…Besides, there also exist research effort s that f ocus on overlay integration and implementation. Wiersema et al [21] propose to embed a ZUMA-based vFPGA architecture into their configurable system-onchip ReconOS. Moreover, in [20] , authors designed a fine grained overlay with extra routing resources to ease the task of their Just-In-Time synthesizer.…”

Section: Fine-grained Overlaysmentioning

confidence: 99%