Embracing the Unreliability of Memory Devices for Neuromorphic Computing

Abstract

The emergence of resistive non-volatile memories opens the way to highly energy-efficient computation near-or in-memory. However, this type of computation is not compatible with conventional ECC, and has to deal with device unreliability. Inspired by the architecture of animal brains, we present a manufactured differential hybrid CMOS/RRAM memory architecture suitable for neural network implementation that functions without formal ECC. We also show that using low-energy but error-prone programming conditions only slightly reduces network accuracy.

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

“…Proactive hardware-based Reactive hardware-based Cross-layer Model training modification [61], [90], [91], [202]- [223] Memory cell re-design [224], [225] Weight-shifting [226] Model/hardware co-design [227], [228] Model modification [229]- [231] Memory aging mitigation [232] Re-learning [233] Fault-aware pruning with retraining [95] Fault-tolerant model search [234] Activation clipping [57], [81], [235]- [238] Algorithmic-based fault-tolerance [81], [239]- [244] Fault-aware mapping [101],…”

“…1) Memory cell re-design: In [224], a passive faulttolerance method for ReRAM-based crossbars is proposed by re-designing the memory cell to have a 2-transistor/2-resistor (2T2R) structure, where each bit of information is stored in a differential fashion. In particular, the pair Low Resistive State (LRS)/High Resistive State (HRS) means logic value zero, while the pair HRS/LRS means logic value one.…”