Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies

Study of Parasitic Effects of 1st Generation in 4T Relay Design

“…In cases such as this, the relay could not be turned off, even after V G is lowered back to zero. As illustrated in 6 (b), the channel potential is also at VDD resulting in electrostatic force between the channel and the body (8). A large overlap area between the channel and the body (A CB ), creates electrostatic force large enough to overpower the spring restoring force (V RL drops to below 0V).…”

Optimal sizing of configurable devices to reduce variability in integrated circuits

“…The reduction of supply voltage leads to a direct loss of headroom when designing analogue circuitswhich in turn impacts on dynamic range, noise and signal integrity. As technologies become smaller, leakage becomes a greater problem in analogue circuits, indeed this is one of the most significant problems for digital design [4]. Variability in process parameters is a far greater problem in DSM nodes especially as device models are reaching their limits of predictability [5].…”

“…In the case of analogue circuits the impact of variability can be complex due to a large number of performance specifications. Traditional approaches to increase robustness and resilience can introduce unacceptable power and area penalties when applied to modern process nodes [4]. Conventional techniques have attempted to mitigate the effects of device variability using a standard robust design approach, but this clearly has limitations, and does not fundamentally address the issue of post-manufacture failure, lifetime degradation and device drift [8], [9], [10].…”

“…This is a particular problem for AMS designs where yield is severely degraded below the 120nm process node as a result of this increasing variability. Recent research has been targeted at analog circuit design as result, to identify potential solutions to this problem from a structural perspective, such as recently by Gielen et al [4]. Variability can be broadly categorized into spatial and temporal effects.…”

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

“…As semiconductor technology continuously scales, the joint effects of manufacture process variations and operational lifetime parameter degradations have been a major concern for analog circuit designers since they affect the lifetime yield value, i.e., the percentage of the products which can satisfy all of the pre-defined specifications during lifetime operation (Alam, Kang, Paul & Roy, 2007), (Gielen et al, 2008). The analysis and optimization of analog circuits considering process variations alone have been in research for decades, and certain design centering algorithms and commercial software are available to achieve a design for yield (more specifically, fresh yield) (Nassif, 2008), (Antreich et al, 1994).…”