Emulation engine for spiking neurons and adaptive synaptic weights

Hellmich, H. H.; Geike, M.; Griep, P.; Mahr, Philipp; Rafanelli, Maurizio; Klär, H.

doi:10.1109/ijcnn.2005.1556450

Cited by 20 publications

(10 citation statements)

References 9 publications

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“…Part of this project is an acceleration board, called SSE, implemented with a collection of FPGAs interconnected via an on-board bus. An SEE accelerator is able to perform neural computations 30 times faster than a desktop PC [12]. Other projects used FPGAs for similar purposes, obtaining speedups of up to 50 compared to software-only implementations.…”

Section: Related Workmentioning

confidence: 99%

Understanding the interconnection network of SpiNNaker

Navaridas

Luján

Miguel-Alonso

et al. 2009

Proceedings of the 23rd International Conference on Supercomputing

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SpiNNaker is a massively parallel architecture designed to model large-scale spiking neural networks in (biological) real-time. Its design is based around ad-hoc multi-core System-on-Chips which are interconnected using a two-dimensional toroidal triangular mesh. Neurons are modeled in software and their spikes generate packets that propagate through the on-and inter-chip communication fabric relying on custom-made on-chip multicast routers. This paper models and evaluates large-scale instances of its novel interconnect (more than 65 thousand nodes, or over one million computing cores), focusing on real-time features and fault-tolerance. The key contribution can be summarized as understanding the properties of the feasible topologies and establishing the stable operation of the SpiNNaker under different levels of degradation. First we derive analytically the topological characteristics of the network, which are later confirmed by experimental work. With the computational model developed, we investigate the topology of SpiNNaker, and compare it with a standard 3-dimensional torus. The novel emergency routing mechanism, implemented within the routers, allows the topology of SpiNNaker to be more robust than the 3-dimensional torus, regardless of the latter having better topological characteristics. Furthermore, we obtain optimal values of two router parameters related with livelock and deadlock avoidance mechanisms.

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Section: Related Workmentioning

confidence: 99%

Understanding the interconnection network of SpiNNaker

Navaridas

Luján

Miguel-Alonso

et al. 2009

Proceedings of the 23rd International Conference on Supercomputing

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“…Several chapters in [99] are dedicated to this subject, and more recent work can be found for instance in [170,53,77,33,125,116,150].…”

Section: Implementing Snnsmentioning

confidence: 99%

Computing with Spiking Neuron Networks

Paugam-Moisy

Bohté

2012

Handbook of Natural Computing

209

114

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Spiking Neuron Networks (SNNs) are often referred to as the 3 rd generation of neural networks. Highly inspired from natural computing in the brain and recent advances in neurosciences, they derive their strength and interest from an accurate modeling of synaptic interactions between neurons, taking into account the time of spike firing. SNNs overcome the computational power of neural networks made of threshold or sigmoidal units. Based on dynamic event-driven processing, they open up new horizons for developing models with an exponential capacity of memorizing and a strong ability to fast adaptation. Today, the main challenge is to discover efficient learning rules that might take advantage of the specific features of SNNs while keeping the nice properties (general-purpose, easy-to-use, available simulators, etc.) of traditional connectionist models. This chapter relates the history of the "spiking neuron" in Section 1 and summarizes the most currently-in-use models of neurons and synaptic plasticity in Section 2. The computational power of SNNs is addressed in Section 3 and the problem of learning in networks of spiking neurons is tackled in Section 4, with insights into the tracks currently explored for solving it. Finally, Section 5 discusses application domains, implementation issues and proposes several simulation frameworks.

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“…GPU acceleration has been explored by many previous work [24]- [26]. Although GPU offers great floating point computing power with massive parallelism, it is not an ideal architecture for neuron simulation.…”

Section: Related Workmentioning

confidence: 99%

FPGA simulation engine for customized construction of neural microcircuits

Blair

Cong

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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In this paper we describe an FPGA-based platform for high-performance and low-power simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Based on high-level synthesis, our platform uses design templates to map hierarchies of neuron model to logic fabrics. This approach bypasses high design complexity and enables easy optimization and design space exploration. We demonstrate the benefits of our platform by simulating a variety of neural microcircuits that perform oscillatory path integration, which evidence suggests may be a critical building block of the navigation system inside a rodent's brain. Experiments show that our FPGA simulation engine for oscillatory neural microcircuits can achieve up to 39× speedup compared to software benchmarks on commodity CPU, and 232× energy reduction compared to embedded ARM core.

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Emulation engine for spiking neurons and adaptive synaptic weights

Cited by 20 publications

References 9 publications

Understanding the interconnection network of SpiNNaker

Understanding the interconnection network of SpiNNaker

Computing with Spiking Neuron Networks

FPGA simulation engine for customized construction of neural microcircuits

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