In this paper, we present a digital system called (SP/sup 2/INN) for simulating very large-scale spiking neural networks (VLSNNs) comprising, e.g., 1000000 neurons with several million connections in total. SP/sup 2/INN makes it possible to simulate VLSNN with features such as synaptic short term plasticity, long term plasticity as well as configurable connections. For such VLSNN the computation of the connectivity including the synapses is the main challenging task besides computing the neuron model. We describe the configurable neuron model of SP/sup 2/INN, before we focus on the computation of the connectivity. Within SP/sup 2/INN, connectivity parameters are stored in an external memory, while the actual connections are computed online based on defined connectivity rules. The communication between the SP/sup 2/INN processor and the external memory represents a bottle-neck for the system performance. We show this problem is handled efficiently by introducing a tag scheme and a target-oriented addressing method. The SP/sup 2/INN processor is described in a high-level hardware description language. We present its implementation in a 0.35 /spl mu/m CMOS technology, but also discuss advantages and drawbacks of implementing it on a field programmable gate array.

The simulation of pulse-coded neural networks (PCNNs) for the evaluation of a biology-oriented image processing performed on general-purpose computers, e. g. PCs or workstations, is still very time-consuming. The main bottle-neck during the simulation is the sequential access to the weight memory for the calculation of the neuron states. A field-programmable gate array (FPGA) based emulation engine, called sipiking Neural Network Emulation Engine (SEE), for spiking neurons and adaptive synaptic weights is presented, that tackles this bottle-neck problem by providing a distributed memory architecture and a high bandwidth to the weight memory. In addition, separated calculations of neuron states and network topology are realized and mapped to dedicated FPGAs. With this approach an effective parallelization of the simulation algorithm is obtained. It is evaluated that the current implementation of SEE operating at a frequency of 50 MHz achieves an acceleration factor of 30 for sparsely connected networks (4-and 8-nearest-neighbor connection schemes) compared to a software implementation running on a stand-alone PC (2.4 GHz CPU and 1 GB RAM main memory).

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Today's field-programmable gate array (FPGA) technology offers a large number of IO pins in order to realize a high bandwidth distributed memory architecture. Our acceleration platform, called Spiking Neural Network Emulation Engine (SEE), makes use of this fact in order to tackle the main bottleneck of memory bandwidth during the simulation of large networks and is capable to treat up to tI9 neurons and more than 800.106 synaptic weights. The incorporated neuron state calculation can be reconfigured in order to consider sparse or dense connection schemes. Performance evaluations have revealed that the simulation time scales with the number of adaptive weights. The SEE architecture promises an acceleration by at least factors of 4 to 8 for laterally full-connected networks compared to simulations executed by a stand-alone PC.

Abstract. Die Simulation von grossen pulscodierten neuronalen Netzen (PCNNs) für die Evaluierung einer biologisch motivierten Bildverarbeitung ist auf Einprozessor-Systemen (PCs oder Workstations) immer noch sehr zeitineffizient. Den Flaschenhals während der Simulation bildet der sequentielle Zugriff auf den Gewichtsspeicher zur Berechnung der Neuronenzustände. Es wird ein Digitalsimulator basierend auf feld-programmierbaren Gate-Arrays (FPGAs) vorgestellt, der dieses Flaschenhals-Problem durch eine verteilte Speicherarchitektur und eine erhöhte Speicherbandbreite angeht und zusätzlich eine getrennte Berechnung von Neuronenzuständen und Netzwerktopologie vorsieht. Somit ist es möglich, den des Simulationsalgorithmus zu erhöhen. Die momentane Implementierung mit einer Taktfrequenz von 50MHz verspricht einen Beschleunigungsfaktor von etwa 30 für eine spärliche Vernetzungsstruktur (Vierer- und Achternachbarschaft) im Vergleich zu einem PC mit einer 2,4GHz CPU und 1GB RAM Arbeitsspeicher.