Re-usable low power DSP IP embedded in an ARM based SoC architecture

Hellmich, H. H.; Erdogan, A.T.; Arslan, Tughrul

doi:10.1049/ic:20000415

Cited by 6 publications

(5 citation statements)

References 4 publications

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“…The AMBA AHB [14] is a new generation of AMBA bus intended to address the requirements of high-performance synthesisable designs. It is a high-performance system backbone bus on which the CPU and other direct memory access (DMA) devices reside.…”

Section: Soc Platform and External Memory Controller Architecturementioning

confidence: 99%

Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Osborne

Erdogan

Arslan³

et al. 2002

IEE Proc., Comput. Digit. Tech.

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Advanced microcontroller bus architecture (AMBA) is rapidly becoming the de facto standard for new system-on-chip (SoC) designs. The bus protocol is complex, making any peripherals that can interface to it valuable intellectual property (IP). This paper presents a lowpower bus encoding architecture which is able to deal with the complex advanced highperformance bus (AHB) protocol within AMBA, which involves multiple burst transfers. The architecture is targeted for a low-power SoC platform to be used in a miniaturised low power application area. The paper describes the SoC platform and the bus encoding architecture, and provides results with a design synthesised at 0.35 mm CMOS technology indicating up to 22% power saving.

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Section: Soc Platform and External Memory Controller Architecturementioning

confidence: 99%

Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Osborne

Erdogan

Arslan³

et al. 2002

IEE Proc., Comput. Digit. Tech.

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“…In comparison to the bus interface design that contains a Virtual Component Interface (VCI) [9], the AMBA interface described in this paper eliminates the VCI overhead. As discussed in [10], it is less efficient to design extra VCI for both the bus interface and DSP IPs.…”

Section: Introductionmentioning

confidence: 99%

Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

Shrivastavastava¹,

Tomar²,

Kalra

2010

2010 International Conference on Computational Intelligence and Communication Networks

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This paper describes a System-on-Chip platform architecture for low power high performance Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus protocol and incorporates a novel interfacing scheme which utilizes the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated to the SoC platform. The paper describes the overall SoC platform architecture and the integration scheme, providing results for area usage and power consumption of the main blocks in the platform with an example of a three DSP core integration case.

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“…and scaling 1 SDRAY (256Mb, 6 It is flexible to append new function units without changing the system architecture and the way to contact with the system. In the near hture we will add some new functions such as dual video decoder and/or with hard disk recorder, compatible with AVCiAVS decoder, and compound with channel decoder.…”

Section: Rgb[56s] Argb[isss]mentioning

confidence: 99%

“…Design methodologies are changing from timing-driven design to platform-based design which gains its productivity by minimizing the amount of custom interface design and focused around a standardized bus architecture [5] [6]. AMBA( Advanced Microcontroller Bus Architecture) represents an open standardized bus architecture [2][3 J. AMBA has a hierarchical architecture including the Advanced High-performance Bus(AHB) which is a high-speed, high-bandwidth multimaster bus and the Advanced Peripheral Bus(APB) which is a simple low-power, low-speed unlocked bus.…”

Section: Introductionmentioning

confidence: 99%

Design of a SoC platform for digital media processing

Yang

Zheng

Chen

Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005.

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In this paper we present the design of a HDTV decoder SoC platform which is integrated with IP cores such as MIPs CPU, HDTV video decoder, video processor, OSD and many peripheral IP devices. Cores can be integrated with the platform through non-glue wrappers. By estimating the bus and memory access bandwith we can manage the data path effectively. It is also much flexible to append new functions without changing the system structure. So the SoC architecture fits a wide application of digital media processing.

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Re-usable low power DSP IP embedded in an ARM based SoC architecture

Cited by 6 publications

References 4 publications

Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

Design of a SoC platform for digital media processing

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