Emulation of an ASIC power and temperature monitor system for FPGA prototyping

Glocker, Elisabeth; Chen, Qingqing; Zaidi, Asheque M.; Schlichtmann, Ulf; Schmitt‐Landsiedel, D.

doi:10.1109/recosoc.2015.7238083

Cited by 2 publications

(3 citation statements)

References 22 publications

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“…Similarly, Bhattacharjee et al [4] evaluate the power consumption based on activity counters. Glocker et al [16,17] present eTPMon, an ASIC power and steady-state temperature emulator for FPGA prototypes. Listl et al [25] extend this approach by a DVFS interface for the power monitor and an emulation of chip aging.…”

Section: Evaluation Approaches For Thermal and Resource Management St...mentioning

confidence: 99%

“…The thermal model of an integrated circuit is commonly expressed by an electrical equivalent RC-circuit, which is implemented in most popular thermal simulators, such as HotSpot [48] and MatEx [35]. In [17] and [16] Glocker et al use this model to generate a lookup table (LUT) that stores the steady-state core temperatures for diferent power consumption values of a multi-core processor. To consider the neighboring efect between adjacent cores, Listl et al [25] use a linear regression model to calculate the steady-state core temperatures at run-time.…”

Section: Asic Temperature Modelling and Emulationmentioning

confidence: 99%

“…Thus, thermal sensors on the FPGA [26ś28,31ś33,47] can not be used to emulate the ASIC behavior. Instead ASIC power and temperature emulation [2ś4, 9,16,17,25,39] is required. However, the existing works either completely neglect DVFS or scale the power consumption independently from the processor speed.…”

Section: Introductionmentioning

confidence: 99%

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An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors

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ACM Trans. Archit. Code Optim.

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The continuous technology scaling of integrated circuits results in increasingly higher power densities and operating temperatures. Hence, modern many-core processors require sophisticated thermal and resource management strategies to mitigate these undesirable side effects. A simulation-based evaluation of these strategies is limited by the accuracy of the underlying processor model and the simulation speed. Therefore, we present, for the first time, an FPGA-based evaluation approach to test and compare thermal and resource management strategies using the combination of benchmark generation, FPGA-based ASIC emulation and run-time monitoring. The proposed benchmark generation method enables an evaluation of run-time management strategies for applications with various run-time characteristics. Furthermore, the ASIC emulation platform features a novel distributed temperature emulator design, whose overhead scales linearly with the number of integrated cores, and a novel dynamic voltage frequency scaling emulator design, which precisely models the timing and energy overhead of voltage and frequency transitions. In our evaluations, we demonstrate the proposed approach for a tiled many-core processor with 80 cores on four Virtex-7 FPGAs. Additionally, we present the suitability of the platform to evaluate state-of-the-art run-time management techniques with a case study.

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