Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

Chen, D.Y.; Chiou, W.C.; Chen, M.F.; Wang, T.D.; Ching, K.M.; Tu, Hongen; Wu, Wenjing; Yu, Chunyang; Yang, Kai-Shing; Chang, Hun-Hsien; Tseng, Ming Hau; Hsiao, Ch.; Lu, Yung Jean; Hu, Hsu-Tien; Lin, Yi; Hsu, C.S.; Shue, W.S.; Yu, C. H.

doi:10.1109/iedm.2009.5424350

Cited by 43 publications

(7 citation statements)

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“…8b). Regarding nowadays high density TSV processes, electrical resistances spread over a certain interval: [9]: 20mΩ-25mΩ; [10]: 350mΩ-400mΩ; [11]: 20mΩ-30mΩ. The 10% failure criterion for a single TSV is thus not relevant compared to process accuracy.…”

Section: Resistance Change Failure Criterion Discussion For Tctmentioning

confidence: 99%

Reliability approach of high density Through Silicon Via (TSV)

Frank

Chappaz

Leduc

et al. 2010

2010 12th Electronics Packaging Technology Conference

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ISBN 978-1-4244-8561-1International audienceThis paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV), and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (EM) tests. Physical analyses reveal the presence of a carbon impurity layer at bottom of the higher resistance TSVs. This impurity induces failure during TCT, but has no impact on EM time to failure distribution. We also discuss the relevance of different electrical resistance failure criterions after TCT for a single TSV

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Section: Resistance Change Failure Criterion Discussion For Tctmentioning

confidence: 99%

Reliability approach of high density Through Silicon Via (TSV)

Frank

Chappaz

Leduc

et al. 2010

2010 12th Electronics Packaging Technology Conference

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“…3-D chip stacking combined with through-silicon vias is a form of SiP that integrates multiple chips into a single package. 3-D + TSV technology provides a high density of vertical chip-chip interconnects along with the small form factor that is needed for mobile and hand-held systems 19,20 . One example of the use of 3-D + TSV technology is shown in Figure 11where a DRAM chip is attached to the top of a CPU logic chip and they are connected together with an array of copper through-silicon vias.…”

Section: Microprocessor Design Innovationsmentioning

confidence: 99%

Moore's Law in the innovation era

Bohr

2011

SPIE Proceedings

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Traditional transistor scaling methods served our industry well for more than three decades until the early 1990s when leakage current and active power constraints threatened to end the continued improvements provided by Moore's Law. The end of the traditional scaling era ushered in the beginning of the innovation era. Process technology innovations such as strained silicon, high-k metal gate transistors, and copper + low-k interconnects have enabled continued performance improvements for scaled devices. Microprocessor design and architecture innovations such as multi-core designs combined with power gates were significant contributors to improved performance and improved power efficiency. Future computing products demand small form factors and long battery life that can be met through a combination of transistor innovation, System-on-Chip and System-in-Package integration techniques.

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“…Multi dies stack using TSV and/or TSI are required for higher performance, greater package miniaturization and more functionality electronic device of 28nm node and below [1,2]. Building and expanding on top of the process knowledge acquired previously for 2-die stack [3], the objective of this paper is to present the thru silicon stacking development works for a 4-die stack fcCSP.…”

Section: Introductionmentioning

confidence: 99%

Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps

Au¹,

Beleran²,

Yang³

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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High performance, multi functional and package miniaturization will be the main driving forces that propel the future trend and development of fully integrated multi silicon dies stack using through silicon via (TSV) packaging technology. This paper serves as an extension of the foregoing paper, where TSV-micro C4 solder interconnect were used and stack up to 4-die compared to the 2-die stack previously demonstrated at ECTC 2010 [3].

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Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

Cited by 43 publications

References 1 publication

Reliability approach of high density Through Silicon Via (TSV)

Reliability approach of high density Through Silicon Via (TSV)

Moore's Law in the innovation era

Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps

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Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

Cited by 43 publications

References 1 publication

Reliability approach of high density Through Silicon Via (TSV)

Reliability approach of high density Through Silicon Via (TSV)

Moore's Law in the innovation era

Thru silicon via stacking &amp; numerical characterization for multi-die interconnections using full array &amp; very fine pitch micro C4 bumps

Contact Info

Product

Resources

About

Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps