High performance, multi functional and package miniaturization will be the main driving forces that propel the future trend and development of fully integrated multi silicon dies stack using through silicon via (TSV) packaging technology. This paper serves as an extension of the foregoing paper, where TSV-micro C4 solder interconnect were used and stack up to 4-die compared to the 2-die stack previously demonstrated at ECTC 2010 [3].

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In this paper, the fundamental understanding of copper (Cu) wire bonding process, and its interaction with the die bond pad surface and structure will be examined, using both Finite Element Analysis (FEA) and experimental study. In the FEA, the Cu wire bonding process is modeled based on dynamic analysis using commercial available finite element software, to investigate the capillary geometry and the bond pad structure designs. In the experimental study, four different factors are evaluated; 1) the inner chamfer angle (ICA) of the capillary, which can affects the ball bond shape formation; 2) the Al pad thickness, and 3) die bond pad coating, which can affects the Al squashing; lastly, 4) the die bond pad structure.

As the progression of 45/40nm ELK devices into mainstream semiconductor assembly manufacturing process increases, the drive to achieve adoption without major changes to process and equipment infrastructure while meeting the superior yield necessary is high. The main goal of this article is to share learning's and provide solutions for integration of 45/40nm ELK devices into Flip Chip and Wire Bond interconnect technology. The scope of this paper covers from FBGA/PBGA for the WB packages and fcCSP for the Flip Chip Devices.The main challenge and focus point for wire bond 45/40nm interconnects is on the 1 st bond process. This paper will share some detailed analysis on the following: WB characterization for 45/40nm ELK ultra-finepitch  Key factors for good ball bond integrity and comparison of Au and Cu wire bond process  Recommendations for achieving the required levels of reliability for 45nm Cu ELK integration. The challenges however, for Flip Chip technology are significantly different from the WB process. More and more adoption is being made from conventional eutectic solder bumps or high-lead solder bumps towards the lead-free solder bumps mainly due to the green initiatives. This paper will share analysis on the following: Thermo-Mechanical Simulation on key input factors and its correlation to actual evaluation results.  Integration of Pb Free ELK Bump with 40nm ELK technology with focus on the critical reflow process.