Enabling a reliable STT-MRAM main memory simulation

Asifuzzaman, Kazi; Verdejo, Rommel Sánchez; Radojković, Petar

doi:10.1145/3132402.3132416

Cited by 17 publications

(21 citation statements)

References 32 publications

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“…Worst-case Read/Write time for these devices is higher than the DRAM device [1,3,6,28]. However, average case read time is less than a DRAM device, which is verified via extensive simulations using popular cycle-accurate memory simulator NVmain [31].…”

Section: Sttmram: Spin-transfer Torque Magnetic Random Access Memorymentioning

confidence: 79%

Towards Enhanced System Efficiency while Mitigating Row Hammer

Goswami

Banerjee

Das

2021

ACM Trans. Archit. Code Optim.

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In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an aggressor row , causes its adjacent rows’ ( victim ) bits to flip. The state-of-the-art solution is to refresh the victim rows explicitly to prevent bit flipping. There have been several proposals made to detect RH attacks. These include both probabilistic as well as deterministic counter-based methods. The technique of handling RH attacks, however, remains the same. In this work, we propose an efficient technique for handling the RH problem. We show that the mechanism is agnostic of the detection mechanism. Our RH handling technique omits the necessity of refreshing the victim rows. Instead, we use a small non-volatile Spin-Transfer Torque Magnetic Random Access Memory (STTRAM) that ensures no unnecessary refreshes of the victim rows on the DRAM device and thus allowing more time for normal applications in the same DRAM device. Our model relies on the migration of the aggressor rows. This accounts for removing blocking of the DRAM operations due to the refreshing of victim rows incurred in the previous solution. After extensive evaluation, we found that, compared to the conventional RH mitigation techniques, our model minimizes the blocking time of the memory that is imposed due to explicit refreshing by an average of 80.72% in the worst-case scenario and provides energy savings of about 15.82% on average, across different types of RH-based workloads. A lookup table is necessary to pinpoint the location of a particular row, which, when combined with the STTMRAM, limits the storage overhead to 0.39% of a 2 GB DRAM. Our proposed model prevents repeated refreshing of the same victim rows in different refreshing windows on the DRAM device and leads to an efficient RH handling technique.

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Section: Sttmram: Spin-transfer Torque Magnetic Random Access Memorymentioning

confidence: 79%

Towards Enhanced System Efficiency while Mitigating Row Hammer

Goswami

Banerjee

Das

2021

ACM Trans. Archit. Code Optim.

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“…We model the STT-MRAM timings based on the parameters that are recently published in collaboration with Everspin Technologies Inc., one of the leading STT-MRAM manufacturers [20]. The published timing parameters enable a reliable methodology to simulate STT-MRAM without releasing confidential information about any product.…”

Section: Main Memory Platformmentioning

confidence: 99%

“…ST-1.2 timing parameters are optimistic and would correspond to major enhancements of the STT-MRAM technology, while ST-2.0 parameters are pessimistic estimations. Simulations performed with these timing parameters give us a reliable range of possible system performance impact for upcoming STT-MRAM main memory devices [20].…”

Section: Main Memory Platformmentioning

confidence: 99%

“…al. [20] also detail the differences between the DRAM and STT-MRAM row operations. a component of the timing simulator.…”

Section: Simulation Infrastructure: Soclib and Dramsim2mentioning

confidence: 99%

“…Asifuzzaman et al [20] also present a detailed analysis of STT-MRAM main memory timing and propose an approach to perform a reliable system level simulation of the memory technology. These parameters are accepted by the community and included into the main DRAMSim2 distribution.…”

Section: Related Workmentioning

confidence: 99%

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STT-MRAM for real-time embedded systems

Asifuzzaman

Fernandez

Radojković

et al. 2019

Proceedings of the International Symposium on Memory Systems

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STT-MRAM is an emerging non-volatile memory quickly approaching DRAM in terms of capacity, frequency and device size. Intensified efforts in STT-MRAM research by the memory manufacturers may indicate a revolution with STT-MRAM memory technology is imminent, and therefore it is essential to perform system level research to explore use-cases and identify computing domains that could benefit from this technology. Special STT-MRAM features such as intrinsic radiation hardness, non-volatility, zero stand-by power and capability to function in extreme temperatures makes it particularly suitable for aerospace, avionics and automotive applications. Such applications often have real-time requirementsthat is, certain tasks must complete within a strict deadline. Analyzing whether this deadline is met requires Worst Case Execution Time (WCET) Analysis, which is a fundamental part of evaluating any real-time system. In this study, we investigate the feasibility of using STT-MRAM in real-time embedded systems by analyzing average system performance impact and WCET implications. CCS CONCEPTS • Computer systems organization → Processors and memory architectures; Embedded systems; • Hardware → Non-volatile memory; • Computing methodologies → Real-time simulation;

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DONUTS: An efficient method for checkpointing in non‐volatile memories

Kruger

Pannain

Azevedo

2023

Concurrency and Computation

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Non-volatile memory (NVM) is an emerging technology being explored as an alternative to DRAM main memory in computing systems because of its persistence, higher storage density, lower energy consumption, and access latency close to DRAM. However, persistent memory systems must ensure data consistency on system failures, a property known as crash consistency. One of the main challenges in these systems is creating efficient checkpointing mechanisms in terms of performance and usability. Thus, it is necessary to remove persistence from the critical execution path and reduce the excessive number of writes to NVM caused by logging operations, resulting in increased memory bandwidth usage. Another limitation is that most proposed mechanisms restrict application source code to programming interfaces based on transactional models, typed as software-based approaches. These factors make it challenging to adopt NVM systems. This article presents a software-transparent mechanism based on dynamic epochs with logging operations via processing-in-memory and checkpoints integrated into the cache replacement policy. Compared to the previous best-performing system, our strategy reduces 50.6% of writes to NVM. Furthermore, it does not increase the average memory bandwidth usage, providing crash consistency with less than 2% runtime overhead.

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Enabling a reliable STT-MRAM main memory simulation

Cited by 17 publications

References 32 publications

Towards Enhanced System Efficiency while Mitigating Row Hammer

Towards Enhanced System Efficiency while Mitigating Row Hammer

STT-MRAM for real-time embedded systems

DONUTS: An efficient method for checkpointing in non‐volatile memories

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