Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip

Abstract

Motivated by the importance of energy consumption in mobile electronics this work describes a methodology developed at ARM for power modeling and energy estimation in complex System-on-Chips (SoCs). The approach is based on developing statistical power models for the system components using regression analysis and extends previous work that has mainly focused on microprocessor cores. The power models are derived from post-layout power-estimation data, after exploring the high-level activity space of each component. The models are then used to conduct an energy analysis based on realistic use cases including web browser benchmarks and multimedia algorithms running on a dual-core processor under Linux. The obtained results show the effects of different hardware configurations on power and energy for a given application and that system level energy consumption analysis can help the design team to make informed architectural trade-offs during the design process.

Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure

“…Moreover, the toggling rate of the on-chip bus becomes one of the main design issues because it dominates the power consumption and degrades the performance due to a complex scalability [4,5]. For example, the existing on-chip buses, such as AHB [6] and AXI [7] from ARM Holdings, Wishbone from Silicore Corporation [8], and OCP from OCP-IP [9], cost much hardware resource in terms of slice/gate count and energy consumption, due to a large number of IO and signal definitions and complicated structures.…”

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

“…Actually, it is an unfeasible task to accurately predict latency of a complicated system by static models. Likewise, the power consumption analysis, such as using some high level power analysis tools [131,180,133] or modeling power analysis [23,171,64,84,49,90], suffers from more inaccuracies without gate-level parameters and switching activities. The high abstraction models are very hard to determine with accuracy in the early development stages.…”

“…Since more than 50% of the total dynamic power dissipation in a processor is due to interconnection [133], the on-chip bus becomes one of the main design issues, which dominates the power consumption and degrades the performance due to its poor scalability. Therefore, a reduced interface complexity and minimal power consumption on-chip bus architecture is necessary to the smart devices.…”

“…For instance, the handshaking or response signal is usually not immediate in a complicated system and the abnormal transfer statuses such as ERROR and RETRY are normally occur in a real on-chip bus. Likewise, the power consumption analysis, such as using some high level power analysis tools [131,180,133] and modeling power analysis [90,23,49], suffers from much more inaccuracy without the gate-level parameters and toggle activities of internal logic, signals, and IOs. It is very hard to determine with accuracy in the early circuit design stage using high abstraction models.…”

“…An earlier stage performance evaluations, such as transfer latency [181] and wire efficiency models [108,88], and several high-level power analysis tools [133,64,90,171,84], allow engineers to design circuits more efficiently, reducing the time costs and risk of error involved in building circuit prototypes. For these mathematical analysis models, large system complexity is a challenge, making the enumeration of the complete design logic difficult, sometimes an unfeasible task.…”