2018
DOI: 10.1587/transinf.2017rcp0004
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Enabling FPGA-as-a-Service in the Cloud with hCODE Platform

Abstract: SUMMARY Major cloud service providers, including Amazon and Microsoft, have started employing field-programmable gate arrays (FPGAs) to build high-performance and low-power-consumption cloud capability. However, utilizing an FPGA-enabled cloud is still challenging because of two main reasons. First, the introduction of software and hardware codesign leads to high development complexity. Second, FPGA virtualization and accelerator scheduling techniques are not fully researched for cluster deployment. In this pa… Show more

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Cited by 12 publications
(8 citation statements)
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“…These regions can be asymmetric as well as symmetric in shape. The asymmetric approach is usually taken to support multiple different sizes of modules without having to reconfigure the entire FPGA [54]. The symmetric approach uses similar or identically sized partial regions (also called 'tiled regions' or 'resource slots').…”
Section: B Shellsmentioning
confidence: 99%
“…These regions can be asymmetric as well as symmetric in shape. The asymmetric approach is usually taken to support multiple different sizes of modules without having to reconfigure the entire FPGA [54]. The symmetric approach uses similar or identically sized partial regions (also called 'tiled regions' or 'resource slots').…”
Section: B Shellsmentioning
confidence: 99%
“…In this way, the resource allocation becomes flexible, as it can reside in one or more neighboring regions, which further minimizes the internal fragmentation, as in [78]. On the other hand, asymmetric regions support the modules of different sizes and save us from reconfiguring the whole FPGA [86] altogether. The connectivity is crucial for every execution model, it can either be host connectivity, or independent connectivity or the hybrid of the two.…”
Section: Shellsmentioning
confidence: 99%
“…Single FPGA [4,76,77,86,87,106,107,109,115,117,118,125] [ 23,25,75,78,79,[84][85][86]89,107] Multiple FPGAs [4,77,87,106,115,117,125] [41,75,78,79]…”
Section: Single Application Multiple Applicationsmentioning
confidence: 99%
“…The role region is usually a dynamically reconfigurable region [8], [9], [13], [5]. Some researchers proposed a static role that would be combined with the static logic and synthesized to get the full FPGA bit stream [10], [22]. Compilers for this approach, compile an application (written in High-level language) into a SW part and FPGA part that executes the user-specified compute-intensive functions (kernels).…”
Section: Related Workmentioning
confidence: 99%