Enabling Full-Size Public-Key Algorithms on 8-Bit Sensor Nodes

Uhsadel, Leif; Pöschmann, Axel; Paar, Christof

doi:10.1007/978-3-540-73275-4_6

Cited by 42 publications

(32 citation statements)

References 11 publications

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“…Code size Scalable RSA ECC Speed record Multi-precision multiplication on 8-bit AVR processors: Gura et al [9] n/a Hutter et al [11] 3.1-7.6 kB (U) Hutter et al (L) [12] 1.5-1.9 kB Hutter et al (U) [12] 3.7-151 kB Liu et al [16] n/a Scott et al [19] n/a Seo et al [21] 3.6-10 kB Uhsadel et al [23] n/a Zhang et al [24] n/a This work (RPS mul) 918 B (L,P)…”

Section: Methodsmentioning

confidence: 99%

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Reverse Product-Scanning Multiplication and Squaring on 8-Bit AVR Processors

Liu

Seo

Groβschädl

et al. 2015

Information and Communications Security

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Abstract. High performance, small code size, and good scalability are important requirements for software implementations of multi-precision arithmetic algorithms to fit resource-limited embedded systems. In this paper, we describe optimization techniques to speed up multi-precision multiplication and squaring on the AVR ATmega series of 8-bit microcontrollers. First, we present a new approach to perform multi-precision multiplication, called Reverse Product Scanning (RPS), that resembles the hybrid technique of Gura et al., but calculates the byte-products in the inner loop in reverse order. The RPS method processes four bytes of the two operands in each iteration of the inner loop and employs two carry-catcher registers to minimize the number of add instructions. We also describe an optimized algorithm for multi-precision squaring based on the RPS technique that is, depending on the operand length, up to 44.3% faster than multiplication. Our AVR Assembly implementations of RPS multiplication and RPS squaring occupy less than 1 kB of code space each and are written in a parameterized fashion so that they can support operands of varying length without recompilation. Despite this high level of flexibility, our RPS multiplication outperforms the looped variant of Hutter et al.'s operand-caching technique and saves between 40 and 51% of code size. We also combine our RPS multiplication and squaring routines with Karatsuba's method to further reduce execution time. When executed on an ATmega128 processor, the "karatsubarized RPS method" needs only 85 k clock cycles for a 1024-bit multiplication (or 48 k cycles for a squaring). These results show that it is possible to achieve high performance without sacrificing code size or scalability.

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Section: Methodsmentioning

confidence: 99%

“…update of a loop counter or execution of a branch instruction) and allows for a specific "tuning" of each iteration (see e.g. [23,19]), which is not possible with "rolled" loops. A second line of research focused on speeding up the innerloop operation, i.e.…”

Section: Introductionmentioning

confidence: 99%

Reverse Product-Scanning Multiplication and Squaring on 8-Bit AVR Processors

Liu

Seo

Groβschädl

et al. 2015

Information and Communications Security

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“…It is known that the dominant cost in EC-based cryptographic operations is point multiplications [10]. On the other hand, modular addition, modular multiplication, SHA-1 and AES operations are roughly three to four orders of magnitude faster than a point multiplication evaluation [31]. Hence, in our analysis, we consider only elliptic curve point multiplication (such as r · P) and elliptic curve double multiplication (such as r · P + w · V).…”

Section: Efficiency Analysismentioning

confidence: 99%

Privacy-Preserving Observation in Public Spaces

Kerschbaum

Lim²

2015

Computer Security -- ESORICS 2015

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Abstract. One method of privacy-preserving accounting or billing in cyber-physical systems, such as electronic toll collection or public transportation ticketing, is to have the user present an encrypted record of transactions and perform the accounting or billing computation securely on them. Honesty of the user is ensured by spot checking the record for some selected surveyed transactions. But how much privacy does that give the user, i.e. how many transactions need to be surveyed? It turns out that due to collusion in mass surveillance all transactions need to be observed, i.e. this method of spot checking provides no privacy at all. In this paper we present a cryptographic solution to the spot checking problem in cyber-physical systems. Users carry an authentication device that authenticates only based on fair random coins. The probability can be set high enough to allow for spot checking, but in all other cases privacy is perfectly preserved. We analyze our protocol for computational efficiency and show that it can be efficiently implemented even on platforms with limited computing resources, such as smart cards and smart phones.

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“…The majority of research focussed on advancing the hybrid multiplication technique or devising more efficient variants of it. An example is the work of Uhsadel et al [37], who improved the handling of carry bits in the hybrid method and managed to achieve an execution time of 2881 cycles for a (160 × 160)-bit multiplication (without modular reduction), which is about 7.3% faster than Gura et al's original implementation (3106 cycles). Zhang et al [43] re-arranged the sequence in which the byte-by-byte multiplications are carried out and measured an execution time of 2846 clock cycles.…”

Section: Past Work On Lightweight Ecc For 8-bit Processorsmentioning

confidence: 99%

Low-Weight Primes for Lightweight Elliptic Curve Cryptography on 8-bit AVR Processors

Liu

Großschädl

Wong

2014

Information Security and Cryptology

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Abstract. Small 8-bit RISC processors and micro-controllers based on the AVR instruction set architecture are widely used in the embedded domain with applications ranging from smartcards over control systems to wireless sensor nodes. Many of these applications require asymmetric encryption or authentication, which has spurred a body of research into implementation aspects of Elliptic Curve Cryptography (ECC) on the AVR platform. In this paper, we study the suitability of a special class of finite fields, the so-called Optimal Prime Fields (OPFs), for a "lightweight" implementation of ECC with a view towards high performance and security. An OPF is a finite field Fp defined by a prime of the form p = u · 2 k + v, whereby both u and v are "small" (in relation to 2 k ) so that they fit into one or two registers of an AVR processor. OPFs have a low Hamming weight, which allows for a very efficient implementation of the modular reduction since only the non-zero words of p need to be processed. We describe a special variant of Montgomery multiplication for OPFs that does not execute any input-dependent conditional statements (e.g. branch instructions) and is, hence, resistant against certain side-channel attacks. When executed on an Atmel ATmega processor, a multiplication in a 160-bit OPF takes just 3237 cycles, which compares favorably with other implementations of 160-bit modular multiplication on an 8-bit processor. We also describe a performance-optimized and a security-optimized implementation of elliptic curve scalar multiplication over OPFs. The former uses a GLV curve and executes in 4.19 M cycles (over a 160-bit OPF), while the latter is based on a Montgomery curve and has an execution time of approximately 5.93 M cycles. Both results improve the state-of-the-art in lightweight ECC on 8-bit processors.

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Enabling Full-Size Public-Key Algorithms on 8-Bit Sensor Nodes

Cited by 42 publications

References 11 publications

Reverse Product-Scanning Multiplication and Squaring on 8-Bit AVR Processors

Reverse Product-Scanning Multiplication and Squaring on 8-Bit AVR Processors

Privacy-Preserving Observation in Public Spaces

Low-Weight Primes for Lightweight Elliptic Curve Cryptography on 8-bit AVR Processors

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