Enabling Quality and Schedule Predictability in SoC Design using HandoffQC

Karmakar, Bhaskar J.; Chakravarty, V. Kalyana; Venkatraman, R.; Rao, J.

doi:10.1109/isqed.2006.59

Cited by 1 publication

(3 citation statements)

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“…Also, we can derive information regarding data interaction between different clock domains to infer multi-clock balancing requirements automatically. We also plan to derive a graphical representation of the clock tree structural reports, which is an important component of design handoff across teams involved in various aspects of chip design: RTL design, design integration, synthesis, physical design and timing analysis [6]. Commercial EDA tools should also extend to such areas to have integrated solutions for design prototyping.…”

Section: Discussionmentioning

confidence: 99%

“…In any case, an understanding 978-1-4244-2953-0/09/$25.00 ©2009 IEEE of the design connectivity is key to ensuring good quality of results (QoR) out of CTS. The criticality of design profil ing including that of the clock tree and the benefi to chipdesign predictability in such cases is highlighted in [6]. Any improvement to the clock tree quality by means of structural modificati ns, floorpla changes and timing constraint changes often come at a cost to overall design closure and need be done early.…”

Section: Motivationmentioning

confidence: 99%

“…While clock connectivity is a key determining factor for overall CTS QoR, design constraints and assumptions on clock tree balancing and floorpla care-abouts also influ ence the overall results. While early RTL structure analysis can help generate design timing constraints either by providing information for constraints development [6] or automatically [4], the same is not necessarily true for deriving CTS specifications…”

Section: Motivationmentioning

confidence: 99%

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Early clock prototyping for design analysis and quality entitlement

Vishweshwara

Venkatraman

Vipul

2009

2009 10th International Symposium on Quality of Electronic Design

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With growing complexity of System on Chip architectures and difficul time to market requirements, early design planning is very important. Design planning for physical design involves the deriving of information, useful to physical implementation of the chip, from the early design information available. Clock tree design and synthesis being a vital part of the design cycle, requires immense planning and experimentation. This paper proposes a way by which key clock tree information can be derived from as early as the register transfer level description of the design. The proposed methodology aids in analysing the clock tree structurally for being friendly to clock tree synthesis. It also enables the prototyping of the clock tree synthesis to understand the overhead it adds to the design. This information can be used to apply corrective feedback to the clock architecture and the physical implementation flo . The various aspects of the clock tree the flo generates along with their utility are presented in the paper with some testcase data. 10th Int'l Symposium on Quality Electronic Design

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Section: Discussionmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

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